Re: [PATCH 0/8] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0

Alex Bennée writes: > Hmm scratch that... it fails in a number of linux-user only builds with: > > /usr/bin/ld: > libqemu-aarch64_be-linux-user.fa.p/linux-user_aarch64_cpu_loop.c.o: in > function `cpu_loop': > /builds/stsquad/qemu/build/../linux-user/aarch64/cpu_loop.c:133: undefined > ref

Re: [PATCH 0/8] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0

Alex Bennée writes: > Keith Packard writes: > >> This series adds support for RISC-V Semihosting, version 0.2 as >> specified here: >> >> https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 >> >> This specification references the ARM semihosting release 2.0 as specified >> h

Re: [PATCH 0/8] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0

Keith Packard writes: > This series adds support for RISC-V Semihosting, version 0.2 as > specified here: > > https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 > > This specification references the ARM semihosting release 2.0 as specified > here: > > https://static.d

[PATCH 0/8] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0

This series adds support for RISC-V Semihosting, version 0.2 as specified here: https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 This specification references the ARM semihosting release 2.0 as specified here: https://static.docs.arm.com/100863/0200/semihosting.pd