On 2022/7/4 下午1:18, Richard Henderson wrote:
On 7/1/22 15:04, Xiaojuan Yang wrote:
By the manual of LoongArch CSR, the VS field(18:16 bits) of
ECFG reg means that the number of instructions between each
exception entry is 2^VS.
Is it a typo in the manual that says "2VS", i.e.
On 7/1/22 15:04, Xiaojuan Yang wrote:
By the manual of LoongArch CSR, the VS field(18:16 bits) of
ECFG reg means that the number of instructions between each
exception entry is 2^VS.
Is it a typo in the manual that says "2VS", i.e. multiplication?
If so,
Reviewed-by: Richard Henderson
r~
By the manual of LoongArch CSR, the VS field(18:16 bits) of
ECFG reg means that the number of instructions between each
exception entry is 2^VS.
Signed-off-by: Xiaojuan Yang
---
target/loongarch/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/loongarch/cpu.c
