On Thu, Jun 16, 2022 at 10:34 AM Alistair Francis wrote:
>
> On Mon, Jun 13, 2022 at 10:30 PM Bin Meng wrote:
> >
> > On Mon, Jun 13, 2022 at 8:33 AM Alistair Francis
> > wrote:
> > >
> > > On Thu, Jun 9, 2022 at 11:08 AM Bin Meng wrote:
> > > >
> > > > env->misa_mxl was already set in the
On Mon, Jun 13, 2022 at 10:30 PM Bin Meng wrote:
>
> On Mon, Jun 13, 2022 at 8:33 AM Alistair Francis wrote:
> >
> > On Thu, Jun 9, 2022 at 11:08 AM Bin Meng wrote:
> > >
> > > env->misa_mxl was already set in the RISC-V cpu init routine, and
> > > validated at the beginning of
On Mon, Jun 13, 2022 at 8:33 AM Alistair Francis wrote:
>
> On Thu, Jun 9, 2022 at 11:08 AM Bin Meng wrote:
> >
> > env->misa_mxl was already set in the RISC-V cpu init routine, and
> > validated at the beginning of riscv_cpu_realize(). There is no need
> > to do a redundant initialization
On Thu, Jun 9, 2022 at 11:08 AM Bin Meng wrote:
>
> env->misa_mxl was already set in the RISC-V cpu init routine, and
> validated at the beginning of riscv_cpu_realize(). There is no need
> to do a redundant initialization later.
>
> Signed-off-by: Bin Meng
> ---
>
> target/riscv/cpu.c | 2 +-
>
env->misa_mxl was already set in the RISC-V cpu init routine, and
validated at the beginning of riscv_cpu_realize(). There is no need
to do a redundant initialization later.
Signed-off-by: Bin Meng
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
