Re: [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)

2021-10-24 Thread Richard Henderson
On 10/24/21 10:37 AM, Richard Henderson wrote: On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote: +static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a, +  enum CPUMIPSMSADataFormat df_base, +  void (*gen_msa_3rf)(TCGv_ptr, TCGv_i32, TCGv_i32,

Re: [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)

2021-10-24 Thread Richard Henderson
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote: +static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a, + enum CPUMIPSMSADataFormat df_base, + void (*gen_msa_3rf)(TCGv_ptr, TCGv_i32, TCGv_i32, +

[PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)

2021-10-23 Thread Philippe Mathieu-Daudé
Convert 3-register floating-point or fixed-point operations to decodetree. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 8 target/mips/tcg/msa_translate.c | 70 +++-- 2 files changed, 39 insertions(+), 39 deletions(-) diff --git a