On Mon, 9 May 2022 at 23:55, ishii.shuuic...@fujitsu.com
wrote:
>
> Hi, Peter.
>
> > Shuuichirou, Itaru: do either of you know the right setting for the A64FX
> > for this? If
> > you can find what the hardware value of the ICC_CTLR_EL3 or ICC_CTLR_EL1
> > register is (more specifically, the PRIB
gt; To: qemu-...@nongnu.org; qemu-devel@nongnu.org
> Cc: Ishii, Shuuichirou/石井 周一郎 ; Itaru Kitayama
>
> Subject: Re: [PATCH 4/5] hw/intc/arm_gicv3: Use correct number of priority
> bits
> for the CPU
>
> On Fri, 6 May 2022 at 17:21, Peter Maydell wrote:
> >
>
Peter,
I’ll talk with Shuichiro this coming Monday (here most of us on vacation),
and get back to you.
Itaru.
On Sat, May 7, 2022 at 1:34 Peter Maydell wrote:
> On Fri, 6 May 2022 at 17:21, Peter Maydell
> wrote:
> >
> > Make the GICv3 set its number of bits of physical priority from the
> > i
On Fri, 6 May 2022 at 17:21, Peter Maydell wrote:
>
> Make the GICv3 set its number of bits of physical priority from the
> implementation-specific value provided in the CPU state struct, in
> the same way we already do for virtual priority bits. Because this
> would be a migration compatibility
Make the GICv3 set its number of bits of physical priority from the
implementation-specific value provided in the CPU state struct, in
the same way we already do for virtual priority bits. Because this
would be a migration compatibility break, we provide a property
force-8-bit-prio which is enable
