Kito Cheng writes:
> Hi Keith:
>
> Thanks for your reply, but it seems like we need some more modification in
> linux-user/riscv/cpu_loop.c to enable that, I guess I should post that in
> mail
> rather than attachment :)
>
> Patch here:
>
> From 2f1eb5825a6dda177d3289106970eab05cb08445 Mon
Kito Cheng writes:
> Hi Keith:
>
> Thanks for your reply, but it seems like we need some more modification in
> linux-user/riscv/cpu_loop.c to enable that, I guess I should post that in
> mail
> rather than attachment :)
Ah, I completely missed the attachment! So sorry. That applies cleanly
Hi Keith:
Thanks for your reply, but it seems like we need some more modification in
linux-user/riscv/cpu_loop.c to enable that, I guess I should post that in mail
rather than attachment :)
Patch here:
>From 2f1eb5825a6dda177d3289106970eab05cb08445 Mon Sep 17 00:00:00 2001
From: Kito Cheng
Kito Cheng writes:
> Hi Keith:
>
> Thanks for the patch, I've verified with newlib semihosting support
> which is contributed by Craig Blackmore from embecosm,
> and I would like to add semihosting to user mode, do you mind add this
> patch into this patch series?
I tried to add that already,
Hi Keith:
Thanks for the patch, I've verified with newlib semihosting support
which is contributed by Craig Blackmore from embecosm,
and I would like to add semihosting to user mode, do you mind add this
patch into this patch series?
On Thu, Nov 26, 2020 at 5:41 AM Keith Packard via wrote:
>
>
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception is
