Re: [PATCH v11 4/5] target/riscv: smstateen check for fcsr

2023-03-28 Thread Mayuresh Chitale
On Fri, Mar 24, 2023 at 7:01 PM liweiwei wrote: > > > On 2022/11/21 07:35, Alistair Francis wrote: > > On Sun, Oct 16, 2022 at 11:09 PM Mayuresh Chitale > > wrote: > >> If smstateen is implemented and sstateen0.fcsr is clear then the floating > >> point > >> operations must return illegal instru

Re: [PATCH v11 4/5] target/riscv: smstateen check for fcsr

2023-03-24 Thread liweiwei
On 2022/11/21 07:35, Alistair Francis wrote: On Sun, Oct 16, 2022 at 11:09 PM Mayuresh Chitale wrote: If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by:

Re: [PATCH v11 4/5] target/riscv: smstateen check for fcsr

2022-11-20 Thread Alistair Francis
On Sun, Oct 16, 2022 at 11:09 PM Mayuresh Chitale wrote: > > If smstateen is implemented and sstateen0.fcsr is clear then the floating > point > operations must return illegal instruction exception or virtual instruction > trap, if relevant. > > Signed-off-by: Mayuresh Chitale > Reviewed-by: Wei

Re: [PATCH v11 4/5] target/riscv: smstateen check for fcsr

2022-11-09 Thread Alistair Francis
On Sun, Oct 16, 2022 at 11:09 PM Mayuresh Chitale wrote: > > If smstateen is implemented and sstateen0.fcsr is clear then the floating > point > operations must return illegal instruction exception or virtual instruction > trap, if relevant. > > Signed-off-by: Mayuresh Chitale > Reviewed-by: Wei

[PATCH v11 4/5] target/riscv: smstateen check for fcsr

2022-10-16 Thread Mayuresh Chitale
If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li --- target/riscv/csr.c| 23