Re: [PATCH v2] target/riscv: Fix Guest Physical Address Translation

2023-04-16 Thread Alistair Francis
On Sat, Apr 8, 2023 at 1:34 AM Irina Ryapolova wrote: > > Before changing the flow check for sv39/48/57. > > According to specification (for Supervisor mode): > Sv39 implementations support a 39-bit virtual address space, divided into 4 > KiB pages. > Instruction fetch addresses and load and stor

Re: [PATCH v2] target/riscv: Fix Guest Physical Address Translation

2023-04-16 Thread Alistair Francis
On Sat, Apr 8, 2023 at 1:34 AM Irina Ryapolova wrote: > > Before changing the flow check for sv39/48/57. > > According to specification (for Supervisor mode): > Sv39 implementations support a 39-bit virtual address space, divided into 4 > KiB pages. > Instruction fetch addresses and load and stor

Re: [PATCH v2] target/riscv: Fix Guest Physical Address Translation

2023-04-08 Thread liweiwei
On 2023/4/7 23:32, Irina Ryapolova wrote: Before changing the flow check for sv39/48/57. According to specification (for Supervisor mode): Sv39 implementations support a 39-bit virtual address space, divided into 4 KiB pages. Instruction fetch addresses and load and store effective addresses,

[PATCH v2] target/riscv: Fix Guest Physical Address Translation

2023-04-07 Thread Irina Ryapolova
Before changing the flow check for sv39/48/57. According to specification (for Supervisor mode): Sv39 implementations support a 39-bit virtual address space, divided into 4 KiB pages. Instruction fetch addresses and load and store effective addresses, which are 64 bits, must have bits 63–39 all