On Fri, Sep 24, 2021 at 10:57 PM Richard Henderson
wrote:
>
> On 9/24/21 2:48 AM, Alistair Francis wrote:
> >> But... more specific to this case. Prior to this, was the exception
> >> handler allowed to
> >> assume anything about the contents of stval? Should the value have been
> >> zero?
On 9/24/21 2:48 AM, Alistair Francis wrote:
But... more specific to this case. Prior to this, was the exception handler
allowed to
assume anything about the contents of stval? Should the value have been zero?
Would it
be wrong to write to stval unconditionally? How does the guest OS know
On Wed, Sep 8, 2021 at 4:48 PM Richard Henderson
wrote:
>
> On 9/8/21 6:54 AM, Alistair Francis wrote:
> > @@ -967,6 +967,16 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> > write_tval = true;
> > tval = env->badaddr;
> > break;
> > +case
On 9/8/21 6:54 AM, Alistair Francis wrote:
@@ -967,6 +967,16 @@ void riscv_cpu_do_interrupt(CPUState *cs)
write_tval = true;
tval = env->badaddr;
break;
+case RISCV_EXCP_ILLEGAL_INST:
+if (riscv_feature(env,
On Wed, Sep 8, 2021 at 12:54 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> The stval and mtval registers can optionally contain the faulting
> instruction on an illegal instruction exception. This patch adds support
> for setting the stval and mtval registers based on the CPU
From: Alistair Francis
The stval and mtval registers can optionally contain the faulting
instruction on an illegal instruction exception. This patch adds support
for setting the stval and mtval registers based on the CPU feature.
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h|
