On 6/25/20 2:12 PM, Lijun Pan wrote:
> Do you mean not submiting the second patch until all the instructions are
> enabled in the future?
Well, I mean not *merging* the second patch until all of the instructions are
enabled.
r~
> On Jun 25, 2020, at 12:40 PM, Richard Henderson
> wrote:
>
> On 6/25/20 10:00 AM, Lijun Pan wrote:
>> +/* POWER ISA 3.1
>> */
>> +PPC2_ISA310= 0x0010ULL,
>
> This goes in the first patch, but...
>
>> #def
On 6/25/20 10:00 AM, Lijun Pan wrote:
> +/* POWER ISA 3.1
> */
> +PPC2_ISA310= 0x0010ULL,
This goes in the first patch, but...
> #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX |
> \
This flag will be used for Power10 instructions.
Signed-off-by: Lijun Pan
---
target/ppc/cpu.h| 4 +++-
target/ppc/translate_init.inc.c | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 1988b436cb..ebb5a0811a 100644
-
