> On Jun 25, 2020, at 12:42 PM, Richard Henderson
> wrote:
>
> On 6/25/20 10:00 AM, Lijun Pan wrote:
>> +static void gen_brh(DisasContext *ctx)
>> +{
>> +TCGv_i64 t0 = tcg_temp_new_i64();
>> +TCGv_i64 t1 = tcg_temp_new_i64();
>> +TCGv_i64 t2 = tcg_temp_new_i64();
>> +
>> +tcg_
On 6/25/20 10:00 AM, Lijun Pan wrote:
> +static void gen_brh(DisasContext *ctx)
> +{
> +TCGv_i64 t0 = tcg_temp_new_i64();
> +TCGv_i64 t1 = tcg_temp_new_i64();
> +TCGv_i64 t2 = tcg_temp_new_i64();
> +
> +tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull);
> +tcg_gen_shri_i64(t1, cpu_gpr
POWER ISA 3.1 introduces following byte-reverse instructions:
brd: Byte-Reverse Doubleword X-form
brw: Byte-Reverse Word X-form
brh: Byte-Reverse Halfword X-form
Signed-off-by: Lijun Pan
---
v3: fix the store issue in br[dwh]
simplify brw implementation
add "if defined(TARGET_PPC64)"
ta
