Hi Cedric,
> From: Cédric Le Goater
> [ ... ]
>
> >> I don't think this is necessary to do so now. Possibly, increase the
> >> version number in the vmstate when resending a v5.
> >>
> > If I understand your request, do you mean to change as following in this
> patch?
> >
> > static const VMState
[ ... ]
I don't think this is necessary to do so now. Possibly, increase the version
number in the vmstate when resending a v5.
If I understand your request, do you mean to change as following in this patch?
static const VMStateDescription vmstate_aspeed_sdmc = {
.name = "aspeed.sdmc",
; Beraldo Leal
> ; open list:ASPEED BMCs ; open
> list:All patches CC here
> Cc: Troy Lee ; Yunlin Tang
>
> Subject: Re: [PATCH v4 05/16] aspeed/sdmc: Add AST2700 support
>
> On 5/28/24 03:26, Jamin Lin wrote:
> > Hi Philippe, Cedric
> >
> >> On 27/5/24 13:18, Cédr
On 5/28/24 03:26, Jamin Lin wrote:
Hi Philippe, Cedric
On 27/5/24 13:18, Cédric Le Goater wrote:
On 5/27/24 12:24, Philippe Mathieu-Daudé wrote:
Hi Jamin,
On 27/5/24 10:02, Jamin Lin wrote:
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up t
Hi Philippe, Cedric
> On 27/5/24 13:18, Cédric Le Goater wrote:
> > On 5/27/24 12:24, Philippe Mathieu-Daudé wrote:
> >> Hi Jamin,
> >>
> >> On 27/5/24 10:02, Jamin Lin wrote:
> >>> The SDRAM memory controller(DRAMC) controls the access to external
> >>> DDR4 and DDR5 SDRAM and power up to DDR4 an
On 27/5/24 13:18, Cédric Le Goater wrote:
On 5/27/24 12:24, Philippe Mathieu-Daudé wrote:
Hi Jamin,
On 27/5/24 10:02, Jamin Lin wrote:
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
The DRAM memory controller of AST270
On 5/27/24 12:24, Philippe Mathieu-Daudé wrote:
Hi Jamin,
On 27/5/24 10:02, Jamin Lin wrote:
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
The DRAM memory controller of AST2700 is not backward compatible
to previous ch
Hi Jamin,
On 27/5/24 10:02, Jamin Lin wrote:
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
The DRAM memory controller of AST2700 is not backward compatible
to previous chips such AST2600, AST2500 and AST2400.
Max memor
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
The DRAM memory controller of AST2700 is not backward compatible
to previous chips such AST2600, AST2500 and AST2400.
Max memory is now 8GiB on the AST2700. Introduce new
aspe
