On 2/21/23 23:37, Daniel Henrique Barboza wrote:
Do you mean that the doc should tell whether the address to be returned in the
store
access fault should be aligned and whatnot?
Yes.
By reading target/riscv code it seems that all store acess faults are being
fired via
raise_mmu_exception(),
On 2/18/23 16:35, Richard Henderson wrote:
On 2/17/23 23:28, Daniel Henrique Barboza wrote:
"A cache-block zero instruction is permitted to access the specified cache
block whenever
a store instruction is permitted to access the corresponding physical addresses
and when
the PMAs indicate th
On 2/17/23 23:28, Daniel Henrique Barboza wrote:
"A cache-block zero instruction is permitted to access the specified cache
block whenever
a store instruction is permitted to access the corresponding physical addresses
and when
the PMAs indicate that cache-block zero instructions are a supporte
On 2023/2/18 04:34, Daniel Henrique Barboza wrote:
From: Christoph Muellner
The RISC-V base cache management operation (CBO) ISA extension has been
ratified. It defines three extensions: Cache-Block Management, Cache-Block
Prefetch and Cache-Block Zero. More information about the spec can be
On 2/18/23 00:44, Richard Henderson wrote:
On 2/17/23 10:34, Daniel Henrique Barboza wrote:
+void helper_cbo_zero(CPURISCVState *env, target_ulong address)
+{
+ RISCVCPU *cpu = env_archcpu(env);
+ uintptr_t ra = GETPC();
+ uint16_t cbozlen;
+ void *mem;
+
+ check_zicbo_envcfg(e
On 2/17/23 10:34, Daniel Henrique Barboza wrote:
+void helper_cbo_zero(CPURISCVState *env, target_ulong address)
+{
+RISCVCPU *cpu = env_archcpu(env);
+uintptr_t ra = GETPC();
+uint16_t cbozlen;
+void *mem;
+
+check_zicbo_envcfg(env, MENVCFG_CBZE, ra);
+
+/* Get the size o
From: Christoph Muellner
The RISC-V base cache management operation (CBO) ISA extension has been
ratified. It defines three extensions: Cache-Block Management, Cache-Block
Prefetch and Cache-Block Zero. More information about the spec can be
found at [1].
Let's start by implementing the Cache-Bl
