On Mon, Oct 18, 2021 at 7:37 PM LIU Zhiwei wrote:
>
> Hi Alistair,
>
> Sorry for the send error. And I have a question about this patch set.
Hello Zhiwei,
>
> Firstly, I totally support the vector v1.0 upstream.
Great!
>
> The concern is how to deal with the v0.7.1 code on QEMU. There are so
Hi Alistair,
Sorry for the send error. And I have a question about this patch set.
Firstly, I totally support the vector v1.0 upstream.
The concern is how to deal with the v0.7.1 code on QEMU. There are some
products based on the vector v0.7.1,
such as D1 SOC from Allwinner and Xuantie CPU
Hi Alistair,
There is some products based on the vector v0.7.1, such as D1 SOC from
Allwinner and Xuantie CPU And we have spent a lot of work to support
vector on QEMU.
Allwinner
On 2021/10/15 下午3:45, frank.ch...@sifive.com wrote:
From: Frank Chang
This patchset implements the vect
On Mon, Oct 18, 2021 at 2:12 PM Alistair Francis
wrote:
> On Mon, Oct 18, 2021 at 4:09 PM Frank Chang
> wrote:
> >
> > On Mon, Oct 18, 2021 at 2:00 PM Alistair Francis
> wrote:
> >>
> >> On Fri, Oct 15, 2021 at 5:48 PM wrote:
> >> >
> >> > From: Frank Chang
> >> >
> >> > This patchset impleme
On Mon, Oct 18, 2021 at 4:09 PM Frank Chang wrote:
>
> On Mon, Oct 18, 2021 at 2:00 PM Alistair Francis wrote:
>>
>> On Fri, Oct 15, 2021 at 5:48 PM wrote:
>> >
>> > From: Frank Chang
>> >
>> > This patchset implements the vector extension v1.0 for RISC-V on QEMU.
>> >
>> > RVV v1.0 spec is now
On Mon, Oct 18, 2021 at 2:00 PM Alistair Francis
wrote:
> On Fri, Oct 15, 2021 at 5:48 PM wrote:
> >
> > From: Frank Chang
> >
> > This patchset implements the vector extension v1.0 for RISC-V on QEMU.
> >
> > RVV v1.0 spec is now fronzen for public review:
> > https://github.com/riscv/riscv-v-
On Fri, Oct 15, 2021 at 5:48 PM wrote:
>
> From: Frank Chang
>
> This patchset implements the vector extension v1.0 for RISC-V on QEMU.
>
> RVV v1.0 spec is now fronzen for public review:
> https://github.com/riscv/riscv-v-spec/releases/tag/v1.0
>
> The port is available here:
> https://github.co
於 2021年10月15日 週五 下午3:48寫道：
> From: Frank Chang
>
> This patchset implements the vector extension v1.0 for RISC-V on QEMU.
>
> RVV v1.0 spec is now fronzen for public review:
> https://github.com/riscv/riscv-v-spec/releases/tag/v1.0
>
> The port is available here:
> https://github.com/sifive/qemu
From: Frank Chang
This patchset implements the vector extension v1.0 for RISC-V on QEMU.
RVV v1.0 spec is now fronzen for public review:
https://github.com/riscv/riscv-v-spec/releases/tag/v1.0
The port is available here:
https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v8
RVV v1.0 can be e
