As per arm specs, if the src and dest register are same, write back
operation is suppressed.
[Specs]
if memop == MemOp_LOAD wback n == t n != 31 then
c = ConstrainUnpredictable();
assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF,
Constraint_NOP};
case c of
when
On 27 November 2014 at 12:15, Gaurav Sharma gauravs.2...@gmail.com wrote:
As per arm specs, if the src and dest register are same, write back
operation is suppressed.
[Specs]
if memop == MemOp_LOAD wback n == t n != 31 then
c = ConstrainUnpredictable();
assert c IN {Constraint_WBSUPPRESS,
I was taking into consideration the behavior of afm, which it seems
suppresses write back.
However, i do get your point on this.
Regards,
Gaurav
On Thu, Nov 27, 2014 at 6:10 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 27 November 2014 at 12:15, Gaurav Sharma gauravs.2...@gmail.com
On 27 November 2014 at 12:49, Gaurav Sharma gauravs.2...@gmail.com wrote:
I was taking into consideration the behavior of afm, which it seems
suppresses write back.
The Fast Models are just one implementation -- like every other
implementation, they have to choose a kind of unpredictable
