On Sun, Nov 12, 2006 at 07:02:55PM +0100, Dirk Behme wrote:
> Daniel Jacobowitz wrote:
> >This is with all of the patches I've posted to the
> >list applied
>
> If patches settle down would be nice to get a list of
> patches or a summary patch to be applied in which order
> against which basis.
> A patch which flushes up to 1/32nd of the jump buffer indiscriminately
> cuts it to 1:11-1:13.
>
> Here's that last patch. It changes the hash function so that entries
> from a particular page are always grouped together in tb_jmp_cache,
> then finds the possibly two affected ranges and memsets
Daniel Jacobowitz wrote:
This is with all of the patches I've posted to the
list applied
If patches settle down would be nice to get a list of
patches or a summary patch to be applied in which order
against which basis. Seems that I mixed up finding the
correct ones in the correct order ;)
On Sun, Nov 12, 2006 at 11:56:35AM -0500, Daniel Jacobowitz wrote:
> ---
> target-mips/cpu.h |3 ++-
> target-mips/exec.h |1 +
> target-mips/helper.c|2 +-
> target-mips/mips-defs.h |1 +
> target-mips/op_helper.c | 43 +--
>
On Sun, Nov 12, 2006 at 02:29:38PM +, Thiemo Seufer wrote:
> JFTR, increasing the TLB size from 16 to 64 entries made no performance
> difference whatsoever.
I suspect that's because we do about as much eviction. Here's a
different approach. Whenever an entry is evicted by tlbwr, the guest
c
Paul Brook wrote:
> > > Other targets have a hardware managed TLB. On a hardware managed TLB the
> > > OS treats it as if it were infinite size, and invalidation only occurs
> > > when a OS changes the mappings. On a software managed TLB "flushes" are
> > > more likely to occur during normal operat
On Sun, Nov 12, 2006 at 10:07:15AM -0500, Daniel Jacobowitz wrote:
> > Actually that gives me an idea. When a TLB entry with a different ASID gets
> > evicted we currently flush that page. This should be a no-op because we
> > already did a full flush when the ASID changed.
>
> Let me see if thi
On Sun, Nov 12, 2006 at 02:44:46PM +, Paul Brook wrote:
> > > Other targets have a hardware managed TLB. On a hardware managed TLB the
> > > OS treats it as if it were infinite size, and invalidation only occurs
> > > when a OS changes the mappings. On a software managed TLB "flushes" are
> > >
> > Other targets have a hardware managed TLB. On a hardware managed TLB the
> > OS treats it as if it were infinite size, and invalidation only occurs
> > when a OS changes the mappings. On a software managed TLB "flushes" are
> > more likely to occur during normal operation as TLB slots are reuse
Paul Brook wrote:
> On Sunday 12 November 2006 11:49, Laurent Desnogues wrote:
> > Daniel Jacobowitz a écrit :
> > > Straight qemu with my previously posted MIPS patches takes 6:13 to
> > > start and reboot a MIPS userspace (through init, so lots of fork/exec).
> > >
> > > Thiemo's patch, which flu
On Sunday 12 November 2006 11:49, Laurent Desnogues wrote:
> Daniel Jacobowitz a écrit :
> > Straight qemu with my previously posted MIPS patches takes 6:13 to
> > start and reboot a MIPS userspace (through init, so lots of fork/exec).
> >
> > Thiemo's patch, which flushes the whole jump buffer, cu
Laurent Desnogues wrote:
> Daniel Jacobowitz a écrit :
> >
> >Straight qemu with my previously posted MIPS patches takes 6:13 to
> >start and reboot a MIPS userspace (through init, so lots of fork/exec).
> >
> >Thiemo's patch, which flushes the whole jump buffer, cuts it to 1:40.
> >
> >A patch whi
Daniel Jacobowitz a écrit :
Straight qemu with my previously posted MIPS patches takes 6:13 to
start and reboot a MIPS userspace (through init, so lots of fork/exec).
Thiemo's patch, which flushes the whole jump buffer, cuts it to 1:40.
A patch which finds the entries which need to be flushed
On Sun, Nov 05, 2006 at 10:38:20AM -0500, Daniel Jacobowitz wrote:
> On Mon, Mar 06, 2006 at 02:59:29PM +, Thiemo Seufer wrote:
> > Hello All,
> >
> > this patch vastly improves TLB performance on MIPS, and probably also
> > on other architectures. I measured a Linux boot-shutdown cycle,
> > i
On Mon, Mar 06, 2006 at 02:59:29PM +, Thiemo Seufer wrote:
> Hello All,
>
> this patch vastly improves TLB performance on MIPS, and probably also
> on other architectures. I measured a Linux boot-shutdown cycle,
> including userland init.
Quoting the whole message since this is from March...
Hello All,
this patch vastly improves TLB performance on MIPS, and probably also
on other architectures. I measured a Linux boot-shutdown cycle,
including userland init.
With minimal jump cache invalidation:
real11m43.429s
user9m51.975s
sys 0m1.375s
64.19 1476.81 1476.81 2055190
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