On 5/3/19 6:13 AM, Peter Maydell wrote:
> On Sat, 13 Apr 2019 at 08:07, Richard Henderson
>> This one does do the right thing, but better to clear the bits on write to
>> NSACR. This lets you avoid the change to fp_exception_el, and the missing
>> change to sve_exception_el.
>
> Hi Richard -- I
On Sat, 13 Apr 2019 at 08:07, Richard Henderson
wrote:
>
> On 4/11/19 5:39 AM, Peter Maydell wrote:
> > +static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri)
> > +{
> > +/*
> > + * For A-profile AArch32 EL3, if NSACR.CP10
> > + * is 0 then HCPTR.{TCP11,TCP10} ignore
On Sun, 14 Apr 2019 at 20:40, Richard Henderson
wrote:
>
> On 4/14/19 8:02 AM, Peter Maydell wrote:
> > There's similar wording for the effect of NSACR on CPACR, so
> > again I think we need to actually make the bits RAZ/WI
> > regardless of their underlying value, not just force them
> > to 0.
>
On 4/14/19 8:02 AM, Peter Maydell wrote:
> There's similar wording for the effect of NSACR on CPACR, so
> again I think we need to actually make the bits RAZ/WI
> regardless of their underlying value, not just force them
> to 0.
I don't see that language for CPACR, just "the corresponding bits in
On Sat, 13 Apr 2019 at 08:07, Richard Henderson
wrote:
>
> On 4/11/19 5:39 AM, Peter Maydell wrote:
> > +static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri)
> > +{
> > +/*
> > + * For A-profile AArch32 EL3, if NSACR.CP10
> > + * is 0 then HCPTR.{TCP11,TCP10} ignore
On 4/11/19 5:39 AM, Peter Maydell wrote:
> +static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri)
> +{
> +/*
> + * For A-profile AArch32 EL3, if NSACR.CP10
> + * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
> + */
> +uint64_t value =
The NSACR register allows secure code to configure the FPU
to be inaccessible to non-secure code. If the NSACR.CP10
bit is set then:
* NS accesses to the FPU trap as UNDEF (ie to NS EL1 or EL2)
* CPACR.{CP10,CP11} behave as if RAZ/WI
* HCPTR.{TCP11,TCP10} behave as if RAO/WI
Note that we do
