On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> +static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a, uint32_t insn)
> +{
> +#if defined(TARGET_RISCV64)
> +REQUIRE_FPU;
> +
> +TCGv t0 = tcg_temp_new();
> +gen_set_rm(ctx, a->rm);
> +gen_helper_fcvt_l_s(t0, cpu_env,
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 70 +
2 files changed, 76 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index
