Re: [Qemu-devel] [PATCH 2/2] target-mips: simplify LWL/LDL mask generation

2015-07-14 Thread Paolo Bonzini
On 14/07/2015 18:45, Aurelien Jarno wrote: >>> > > >>> > > mask = 0x7fffull >> (t1 ^ 63) >>> > > >>> > > It's simpler to generate it by doing: >>> > > >>> > > mask = (1 << t1) - 1 >> > >> > Using ~(-1 << t1) may let you use an ANDN instruction, and is also the >> > same nu

Re: [Qemu-devel] [PATCH 2/2] target-mips: simplify LWL/LDL mask generation

2015-07-14 Thread Aurelien Jarno
On 2015-07-14 18:17, Paolo Bonzini wrote: > > > On 14/07/2015 17:45, Aurelien Jarno wrote: > > The LWL/LDL instructions mask the GPR with a mask depending on the > > address alignement. It is currently computed by doing: > > > > mask = 0x7fffull >> (t1 ^ 63) > > > > It's simpler

Re: [Qemu-devel] [PATCH 2/2] target-mips: simplify LWL/LDL mask generation

2015-07-14 Thread Paolo Bonzini
On 14/07/2015 17:45, Aurelien Jarno wrote: > The LWL/LDL instructions mask the GPR with a mask depending on the > address alignement. It is currently computed by doing: > > mask = 0x7fffull >> (t1 ^ 63) > > It's simpler to generate it by doing: > > mask = (1 << t1) - 1 Usi

[Qemu-devel] [PATCH 2/2] target-mips: simplify LWL/LDL mask generation

2015-07-14 Thread Aurelien Jarno
The LWL/LDL instructions mask the GPR with a mask depending on the address alignement. It is currently computed by doing: mask = 0x7fffull >> (t1 ^ 63) It's simpler to generate it by doing: mask = (1 << t1) - 1 It uses the same number of TCG instructions, but it avoids a 32/