Re: [Qemu-devel] [PATCH 3/7] target/arm/translate-a64: Don't underdecode SIMD ld/st multiple

2019-01-28 Thread Laurent Desnogues
On Fri, Jan 25, 2019 at 7:26 PM Peter Maydell wrote: > > In the AdvSIMD load/store multiple structures encodings, > the non-post-indexed case should have zeroes in [20:16] > (which is the Rm field for the post-indexed case). > Correctly UNDEF the currently unallocated encodings which > have

[Qemu-devel] [PATCH 3/7] target/arm/translate-a64: Don't underdecode SIMD ld/st multiple

2019-01-25 Thread Peter Maydell
In the AdvSIMD load/store multiple structures encodings, the non-post-indexed case should have zeroes in [20:16] (which is the Rm field for the post-indexed case). Correctly UNDEF the currently unallocated encodings which have non-zeroes in those bits. Reported-by: Laurent Desnogues