On 04/10/2018 08:13 AM, Peter Maydell wrote:
> On 9 April 2018 at 23:09, Richard Henderson wrote:
>> On 04/09/2018 08:38 PM, Peter Maydell wrote:
>>> +#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
>>> tcg_set_insn_param(s->insn_start, 2, syn);
>>> +#else
>>> +/* tcg_gen_insn_start has split
On 9 April 2018 at 23:09, Richard Henderson wrote:
> On 04/09/2018 08:38 PM, Peter Maydell wrote:
>> +#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
>> tcg_set_insn_param(s->insn_start, 2, syn);
>> +#else
>> +/* tcg_gen_insn_start has split every target_ulong argument to
>> + * op_insn_s
On 04/09/2018 08:38 PM, Peter Maydell wrote:
> +#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
> tcg_set_insn_param(s->insn_start, 2, syn);
> +#else
> +/* tcg_gen_insn_start has split every target_ulong argument to
> + * op_insn_start into two 32-bit arguments, so we want the low
> +
For the Arm target, we have a 3-operand tcg_insn_start,
where the 3 arguments are the PC, condexec bits, and
a syndrome value. We set it up like this:
tcg_gen_insn_start(dc->pc,
(dc->condexec_cond << 4) | (dc->condexec_mask >> 1),
0);
dc->insn_