Hi,
I cherry-picked this patch and the other one implementing
CP0.Config3.CMGCRBase into my series for the Cluster Power Control needs:
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03296.html
I think all issues pointed out during the review for these two patches
have been addressed
On 30 October 2015 at 11:40, James Hogan wrote:
> On Fri, Oct 30, 2015 at 12:36:07AM +, James Hogan wrote:
>> Hi Yongbok,
>>
>> > +case GCR_GIC_BASE_OFS:
>> > +return gcr->gic_base;
>
> Note also, that this is a read-write register. It starts undefined and
> the kernel will write t
On Fri, Oct 30, 2015 at 12:36:07AM +, James Hogan wrote:
> Hi Yongbok,
>
> On Tue, Oct 27, 2015 at 05:12:35PM +, Yongbok Kim wrote:
> > Add part of GCR Block which Linux Kernel utilises and it is enough
> > to bring the GIC up.
> > It defines full 32 Kbytes address space allocated for GCR
Hi Yongbok,
On Tue, Oct 27, 2015 at 05:12:35PM +, Yongbok Kim wrote:
> Add part of GCR Block which Linux Kernel utilises and it is enough
> to bring the GIC up.
> It defines full 32 Kbytes address space allocated for GCR but only few
> registers are implemented such as config, revision, status
Add part of GCR Block which Linux Kernel utilises and it is enough
to bring the GIC up.
It defines full 32 Kbytes address space allocated for GCR but only few
registers are implemented such as config, revision, status, L2 config and
local config registers.
To support MIPS Coherent Manager, this mod
