Re: [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext

2019-01-24 Thread Alistair Francis
On Thu, Jan 24, 2019 at 4:37 PM Palmer Dabbelt wrote: > > On Tue, 15 Jan 2019 14:25:44 PST (-0800), alistai...@gmail.com wrote: > > On Tue, Jan 15, 2019 at 2:24 PM Richard Henderson > > wrote: > >> > >> On 1/15/19 10:58 AM, Alistair Francis wrote: > >> > -static void riscv_tr_init_disas_context(D

Re: [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext

2019-01-24 Thread Palmer Dabbelt
On Tue, 15 Jan 2019 14:25:44 PST (-0800), alistai...@gmail.com wrote: On Tue, Jan 15, 2019 at 2:24 PM Richard Henderson wrote: On 1/15/19 10:58 AM, Alistair Francis wrote: > -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > +static void riscv_tr_init_disas_con

Re: [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext

2019-01-15 Thread Alistair Francis
On Tue, Jan 15, 2019 at 2:24 PM Richard Henderson wrote: > > On 1/15/19 10:58 AM, Alistair Francis wrote: > > -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState > > *cs) > > +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState > > *cpu) > > Why cha

Re: [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext

2019-01-15 Thread Richard Henderson
On 1/15/19 10:58 AM, Alistair Francis wrote: > -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState > *cs) > +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState > *cpu) Why change this? I know there is variation in the naming, but my preferred defa

[Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext

2019-01-14 Thread Alistair Francis
The gen methods should access state from DisasContext. Add priv_ver field to the DisasContext struct. Signed-off-by: Alistair Francis --- target/riscv/translate.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c inde