Re: [Qemu-devel] [PATCH v2] target-mips: generate fences

2016-09-12 Thread Richard Henderson
On 09/09/2016 01:49 AM, Leon Alrae wrote: Actually the lightweight variants of SYNC exist also in earlier revisions of MIPS architecture; therefore this can be tested for example on mips32r2. According to manuals the support is optional, and if given CPU doesn't implement lightweight SYNCs (i.e.

Re: [Qemu-devel] [PATCH v2] target-mips: generate fences

2016-09-09 Thread Leon Alrae
On Thu, Sep 08, 2016 at 10:04:05AM -0700, Richard Henderson wrote: > > +static void gen_sync(int stype) > > +{ > > +TCGOrder tcg_mo = TCG_BAR_SC; > > + > > +switch (stype) { > > +case 0x4: /* SYNC_WMB */ > > +tcg_mo |= TCG_MO_ST_ST; > > +break; > > +case 0x10: /* SYN

Re: [Qemu-devel] [PATCH v2] target-mips: generate fences

2016-09-08 Thread Richard Henderson
On 09/08/2016 03:01 AM, Leon Alrae wrote: > Make use of memory barrier TCG opcode in MIPS front end. > > Signed-off-by: Leon Alrae > --- > v2: > * generate weaker barriers according to stype > --- > target-mips/translate.c | 32 ++-- > 1 file changed, 30 insertions(+)

[Qemu-devel] [PATCH v2] target-mips: generate fences

2016-09-08 Thread Leon Alrae
Make use of memory barrier TCG opcode in MIPS front end. Signed-off-by: Leon Alrae --- v2: * generate weaker barriers according to stype --- target-mips/translate.c | 32 ++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/target-mips/translate.c b/tar