Re: [Qemu-devel] [PATCH v3 13/28] riscv: sifive_e: prci: Update the PRCI register block size

2019-08-11 Thread Alistair Francis
On Sun, Aug 11, 2019 at 1:11 AM Bin Meng wrote: > > Currently the PRCI register block size is set to 0x8000, but in fact > 0x1000 is enough, which is also what the manual says. > > Signed-off-by: Bin Meng > Reviewed-by: Chih-Min Chao Reviewed-by: Alistair Francis Alistair > --- > > Changes i

[Qemu-devel] [PATCH v3 13/28] riscv: sifive_e: prci: Update the PRCI register block size

2019-08-11 Thread Bin Meng
Currently the PRCI register block size is set to 0x8000, but in fact 0x1000 is enough, which is also what the manual says. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao --- Changes in v3: None Changes in v2: None hw/riscv/sifive_e_prci.c | 2 +- include/hw/riscv/sifive_e_prci.h |