On Sun, 9 Sep 2012, Matthew Ogilvie wrote:
Intel's definition of edge triggered means: asserted with a
low-to-high transition at the time an interrupt is registered and
then kept high until the interrupt is served via one of the
EOI mechanisms or goes away unhandled.
So the only difference
On Mon, Nov 19, 2012 at 04:28:31PM +0100, BALATON Zoltan wrote:
On Sun, 9 Sep 2012, Matthew Ogilvie wrote:
Intel's definition of edge triggered means: asserted with a
low-to-high transition at the time an interrupt is registered and
then kept high until the interrupt is served via one of
On 2012-09-11 06:32, Matthew Ogilvie wrote:
On Mon, Sep 10, 2012 at 11:09:27AM +0200, Jan Kiszka wrote:
On 2012-09-10 10:56, Avi Kivity wrote:
On 09/10/2012 04:27 AM, Matthew Ogilvie wrote:
Intel's definition of edge triggered means: asserted with a
low-to-high transition at the time an
On 09/10/2012 04:09 PM, Maciej W. Rozycki wrote:
No, this is about the PIC, not the CPU interrupt inputs.
I see, the interrupt is still sent to the processor; but IRR reflects
that status of the input line, not a pending interrupt status.
Not really, this is still a pending interrupt
On 09/11/2012 12:05 PM, Jan Kiszka wrote:
I think this is convincing, maybe worth documenting in the related
changelogs of QEMU and KVM. Avi, doubts remaining?
Nope, I think I've understood it finally.
--
error compiling committee.c: too many arguments to function
On 09/10/2012 04:27 AM, Matthew Ogilvie wrote:
Intel's definition of edge triggered means: asserted with a
low-to-high transition at the time an interrupt is registered and
then kept high until the interrupt is served via one of the
EOI mechanisms or goes away unhandled.
So the only
On 2012-09-10 10:56, Avi Kivity wrote:
On 09/10/2012 04:27 AM, Matthew Ogilvie wrote:
Intel's definition of edge triggered means: asserted with a
low-to-high transition at the time an interrupt is registered and
then kept high until the interrupt is served via one of the
EOI mechanisms or
On 09/10/2012 12:09 PM, Jan Kiszka wrote:
On 2012-09-10 10:56, Avi Kivity wrote:
On 09/10/2012 04:27 AM, Matthew Ogilvie wrote:
Intel's definition of edge triggered means: asserted with a
low-to-high transition at the time an interrupt is registered and
then kept high until the interrupt is
On 2012-09-10 11:18, Avi Kivity wrote:
On 09/10/2012 12:09 PM, Jan Kiszka wrote:
On 2012-09-10 10:56, Avi Kivity wrote:
On 09/10/2012 04:27 AM, Matthew Ogilvie wrote:
Intel's definition of edge triggered means: asserted with a
low-to-high transition at the time an interrupt is registered and
On Mon, 10 Sep 2012, Avi Kivity wrote:
So the only difference between edge triggered and level triggered
is in the leading edge, with no difference in the trailing edge.
Hard to believe. So an edge while cpu interrupts are disabled is ignored?
Please note that x86 CPU's INT input is
On Mon, Sep 10, 2012 at 11:09:27AM +0200, Jan Kiszka wrote:
On 2012-09-10 10:56, Avi Kivity wrote:
On 09/10/2012 04:27 AM, Matthew Ogilvie wrote:
Intel's definition of edge triggered means: asserted with a
low-to-high transition at the time an interrupt is registered and
then kept high
Intel's definition of edge triggered means: asserted with a
low-to-high transition at the time an interrupt is registered and
then kept high until the interrupt is served via one of the
EOI mechanisms or goes away unhandled.
So the only difference between edge triggered and level triggered
is in
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