Re: [Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exceptions without info

2018-04-26 Thread Alistair Francis
On Wed, Apr 25, 2018 at 4:59 PM Michael Clark wrote: > mtval/stval must be set on all exceptions but zero is > a legal value if there is no exception specific info. > Placing the instruction bytes for illegal instruction > exceptions in mtval/stval is an optional feature and >

[Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exceptions without info

2018-04-25 Thread Michael Clark
mtval/stval must be set on all exceptions but zero is a legal value if there is no exception specific info. Placing the instruction bytes for illegal instruction exceptions in mtval/stval is an optional feature and is currently not supported by QEMU RISC-V. Cc: Sagar Karandikar