Paul Brook wrote:
It should be good to have a well-defined modular IRQ routing
architecture in the Qemu.
We've got most of one for the ARM targets (see hw/arm_pic.h). This file
contains both the target independent bits and the ARM specific bits for
emulating the CPU IRQ/FIQ pins.
Annother
Alexander Voropay a écrit :
> "Aurelien Jarno" <[EMAIL PROTECTED]> wrote:
>
>> Then after playing with the current code, I am sure we are missing a
>> simple interrupt controller for the MIPS CPU. It supports 6 hardware
>> interrupts (IP2 to IP7) and we are using two of them in the current
>> emul
> It should be good to have a well-defined modular IRQ routing
> architecture in the Qemu.
We've got most of one for the ARM targets (see hw/arm_pic.h). This file
contains both the target independent bits and the ARM specific bits for
emulating the CPU IRQ/FIQ pins.
Annother possibility to abst
"Aurelien Jarno" <[EMAIL PROTECTED]> wrote:
Then after playing with the current code, I am sure we are missing a
simple interrupt controller for the MIPS CPU. It supports 6 hardware
interrupts (IP2 to IP7) and we are using two of them in the current
emulation: one for the i8259a and the other fo
On Tue, 23 Jan 2007, Aurelien Jarno wrote:
> There is currently a bug concerning the IRQ acknowlege on the MIPS
> system emulation. It concerns both the QEMU and Malta boards, though it
> is only detectable with a 2.4 kernel and thus on the Malta board. The
> symptom is a storm of "We got a spurio
Hi all,
Some news on that point.
After a discussion with Paul Brook, Thiemo Seufer and Ralf Baechle on
IRC yesterday, we got convinced that the current IRQ handling is not
correct.
The hardware interrupt is currently deasserted by the CPU itself (in
cpu-exec.c). It should be deasserted by the in
Hi all,
There is currently a bug concerning the IRQ acknowlege on the MIPS
system emulation. It concerns both the QEMU and Malta boards, though it
is only detectable with a 2.4 kernel and thus on the Malta board. The
symptom is a storm of "We got a spurious interrupt from PIIX4."
This is due to t
