On 6 October 2011 11:16, Andreas Färber wrote:
> Am 02.10.2011 23:44, schrieb Peter Maydell:
>> On 2 October 2011 19:56, Andreas Färber wrote:
>>> 1) Currently, -cpu is used to look up a Main ID Register value and to base
>>> feature decisions on that. This doesn't work for Cortex-R4 and Cortex-R
Am 02.10.2011 23:44, schrieb Peter Maydell:
> On 2 October 2011 19:56, Andreas Färber wrote:
>> I've been looking into adding support for Cortex-R4F.
>
> Ooh, that will be the first R profile core. In particular the only
> other non-M-profile PMSA core we support is the 946 which was a v5
> core,
On 2 October 2011 22:44, Peter Maydell wrote:
> R4F is going to want V4T, V5, V6, V7, THUMB2, MPU, VFP3, VFP_FP16
> and DIV [although since R profile has UDIV and SDIV only in Thumb
> mode and I've just sent patches that make the DIV feature enable
> it for ARM mode too we'll need to sort that out
On 2 October 2011 19:56, Andreas Färber wrote:
> I've been looking into adding support for Cortex-R4F.
Ooh, that will be the first R profile core. In particular the only
other non-M-profile PMSA core we support is the 946 which was a v5
core, so you'll need to check that we actually implement v7
Hello Peter,
I've been looking into adding support for Cortex-R4F.
1) Currently, -cpu is used to look up a Main ID Register value and to base
feature decisions on that. This doesn't work for Cortex-R4 and Cortex-R4F,
which have an identical MIDR but only -R4F has the FPU.
Re-checking the model st
