On Thu, Jan 7, 2016 at 11:22 AM, Peter Maydell wrote:
> On 7 January 2016 at 10:21, alvise rigo wrote:
>> Hi,
>>
>> On Wed, Jan 6, 2016 at 7:00 PM, Andrew Baumann
>> wrote:
>>> As a heads up, we just added support for alignment checks in LDREX:
>>> https://github.com/qemu/qemu/commit/30901475b91
Hi,
On Wed, Jan 6, 2016 at 7:00 PM, Andrew Baumann
wrote:
>
> Hi,
>
> > From: qemu-devel-bounces+andrew.baumann=microsoft@nongnu.org
> > [mailto:qemu-devel-
> > bounces+andrew.baumann=microsoft@nongnu.org] On Behalf Of
> > Alvise Rigo
> > Sent: Monday, 14 December 2015 00:41
> >
> > This
Hi,
> From: qemu-devel-bounces+andrew.baumann=microsoft@nongnu.org
> [mailto:qemu-devel-
> bounces+andrew.baumann=microsoft@nongnu.org] On Behalf Of
> Alvise Rigo
> Sent: Monday, 14 December 2015 00:41
>
> This is the sixth iteration of the patch series which applies to the
> upstream bra
Hi Alex,
On Thu, Dec 17, 2015 at 5:06 PM, Alex Bennée wrote:
>
> Alvise Rigo writes:
>
> > This is the sixth iteration of the patch series which applies to the
> > upstream branch of QEMU (v2.5.0-rc3).
> >
> > Changes versus previous versions are at the bottom of this cover letter.
> >
> > The
Alvise Rigo writes:
> This is the sixth iteration of the patch series which applies to the
> upstream branch of QEMU (v2.5.0-rc3).
>
> Changes versus previous versions are at the bottom of this cover letter.
>
> The code is also available at following repository:
> https://git.virtualopensystems
On Tue, Dec 15, 2015 at 3:18 PM, Paolo Bonzini wrote:
>
>
> On 15/12/2015 14:59, alvise rigo wrote:
>>> > If we have two CPUs, with CPU 0 executing LL and the CPU 1 executing a
>>> > store, you can model this as a consensus problem. For example, CPU 0
>>> > could propose that the subsequent SC su
On 15/12/2015 14:59, alvise rigo wrote:
>> > If we have two CPUs, with CPU 0 executing LL and the CPU 1 executing a
>> > store, you can model this as a consensus problem. For example, CPU 0
>> > could propose that the subsequent SC succeeds, while CPU 1 proposes that
>> > it fails. The outcome
Hi Paolo,
On Mon, Dec 14, 2015 at 11:17 AM, Paolo Bonzini wrote:
>
>
> On 14/12/2015 11:04, alvise rigo wrote:
>> In any case, what I proposed in the mttcg based v5 was:
>> - A LL ensures that the TLB_EXCL flag is set on all the CPU's TLB.
>> This is done by querying a TLB flush to all (not exact
Hi Andreas,
On Mon, Dec 14, 2015 at 11:09 PM, Andreas Tobler wrote:
> Alvise,
>
> On 14.12.15 09:41, Alvise Rigo wrote:
>>
>> This is the sixth iteration of the patch series which applies to the
>> upstream branch of QEMU (v2.5.0-rc3).
>>
>> Changes versus previous versions are at the bottom of t
Alvise,
On 14.12.15 09:41, Alvise Rigo wrote:
This is the sixth iteration of the patch series which applies to the
upstream branch of QEMU (v2.5.0-rc3).
Changes versus previous versions are at the bottom of this cover letter.
The code is also available at following repository:
https://git.virt
On 14/12/2015 11:04, alvise rigo wrote:
> In any case, what I proposed in the mttcg based v5 was:
> - A LL ensures that the TLB_EXCL flag is set on all the CPU's TLB.
> This is done by querying a TLB flush to all (not exactly all...) the
> CPUs. To be 100% safe, probably we should also wait that
Hi Paolo,
Thank you for your feedback.
On Mon, Dec 14, 2015 at 10:33 AM, Paolo Bonzini wrote:
>
>
>
> On 14/12/2015 09:41, Alvise Rigo wrote:
> > In theory, the provided implementation of TCG LoadLink/StoreConditional
> > can be used to properly handle atomic instructions on any architecture.
>
On 14/12/2015 09:41, Alvise Rigo wrote:
> In theory, the provided implementation of TCG LoadLink/StoreConditional
> can be used to properly handle atomic instructions on any architecture.
No, _in theory_ this implementation is wrong. If a normal store can
make a concurrent LL-SC pair fail, it's
This is the sixth iteration of the patch series which applies to the
upstream branch of QEMU (v2.5.0-rc3).
Changes versus previous versions are at the bottom of this cover letter.
The code is also available at following repository:
https://git.virtualopensystems.com/dev/qemu-mt.git
branch:
slowpa
14 matches
Mail list logo
