Re: [Qemu-devel] Timer interrupts for -M raspi2

Hi Antonio, > From: Antonio Huete Jiménez [mailto:tuxi...@quantumachine.net] > Sent: Wednesday, 16 March 2016 3:40 PM > > Hi, > > I am experiencing what I think it's an issue with -M raspi2 and > interrupts in a baremetal application. > > According to this document >

Re: [Qemu-devel] Timer interrupts for -M raspi2

Hi Antonio, > From: Antonio Huete Jiménez [mailto:tuxi...@quantumachine.net] > Sent: Wednesday, 16 March 2016 4:24 PM > > Hi Andrew, > > I thought the timer that was not implemented was the local timer > (located at 0x4034) and that the core timers interrupt control > registers starting at

Re: [Qemu-devel] Timer interrupts for -M raspi2

Hi Andrew, I thought the timer that was not implemented was the local timer (located at 0x4034) and that the core timers interrupt control registers starting at 0x4040 were the per-core timers. Can you please point me to the documentation about this ARM per-core timers? Thanks,

[Qemu-devel] Timer interrupts for -M raspi2

Hi, I am experiencing what I think it's an issue with -M raspi2 and interrupts in a baremetal application. According to this document (https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf), and if I understood it correctly, you can enable timer interrupts

Re: [Qemu-devel] Timer interrupts for -M raspi2

On 16 March 2016 at 23:40, Andrew Baumann wrote: > Yes, that should work. Bits 0 and 3 are wired up to what qemu refers to as > GTIMER_PHYS and GTIMER_VIRT respectively. (The other two timers aren't > currently connected; I can't remember if that's because they

Re: [Qemu-devel] Timer interrupts for -M raspi2

Hi Andrew, Yeah, that's what I think. I believe I must be overlooking something but I just can't find what. With regards to the ARM Generic timer, I have set the enable bit[0] for CNTP_CTL and also I've set CNTP_TVAL, that's why I think the interrupt is triggered on the real hardware.