On 11/30/19 9:45 AM, Alex Bennée wrote:
> Rather than having a static buffer replace str_buf with a GString
> which we know can grow on demand. Convert the internal functions to
> take a GString instead of a char * and length.
>
> Signed-off-by: Alex Bennée
> Reviewed-by: Richard Henderson
>
On 03/12/19 14:16, Thomas Huth wrote:
> On 03/12/2019 14.04, Paolo Bonzini wrote:
>> On 03/12/19 10:15, Thomas Huth wrote:
>> Maybe we can rename this as read_boot_order_mm, and the previous
>> read_boot_order_pc as read_boot_order_io.
>
> I don't think it makes much sense. This
On 03/12/19 1:47 PM, Geert Uytterhoeven wrote:
> Hi Harish,
>
> On Tue, Dec 3, 2019 at 6:42 AM Harish Jenny K N
> wrote:
>>> +static int gpio_aggregator_probe(struct platform_device *pdev)
>>> +{
>>> + struct device *dev = >dev;
>>> + struct gpio_desc **descs;
>>> + struct
> +static int gpio_aggregator_probe(struct platform_device *pdev)
> +{
> + struct device *dev = >dev;
> + struct gpio_desc **descs;
> + struct gpiochip_fwd *fwd;
> + int i, n;
> +
> + n = gpiod_count(dev, NULL);
> + if (n < 0)
> + return n;
> +
> + descs =
Hi Philippe.
I copied Richard's file and modified it's content, that's why Richard is
there.
Regards,
Michael Rolnik
On Tue, Dec 3, 2019 at 1:18 PM Philippe Mathieu-Daudé
wrote:
> On 12/2/19 8:04 AM, Michael Rolnik wrote:
> > Aleksandar.
> >
> > If this code is going to be merge in 2019 I
On 27/11/19 2:12 PM, Geert Uytterhoeven wrote:
> Add a maintainership section for the GPIO Aggregator/Repeater, covering
> documentation, Device Tree bindings, and driver source code.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> Harish: Do you want to be listed as maintainer, too?
Yes.
Cleber Rosa writes:
> RFC: QEMU Gating CI
> ===
>
> This RFC attempts to address most of the issues described in
> "Requirements/GatinCI"[1]. An also relevant write up is the "State of
> QEMU CI as we enter 4.0"[2].
>
> The general approach is one to minimize the
On 27/11/19 2:12 PM, Geert Uytterhoeven wrote:
> Add Device Tree bindings for a GPIO repeater, with optional translation
> of physical signal properties. This is useful for describing explicitly
> the presence of e.g. an inverter on a GPIO line, and was inspired by the
> non-YAML gpio-inverter
11.11.2019 19:02, Max Reitz wrote:
> Add two tests to see that you cannot replace a Quorum child with the
> mirror job while the child is in use by a different parent.
>
> Signed-off-by: Max Reitz
Reviewed-by: Vladimir Sementsov-Ogievskiy
--
Best regards,
Vladimir
On 12/3/19 1:42 PM, Peter Maydell wrote:
>> +static int allocation_tag_from_addr(uint64_t ptr)
>> +{
>> +ptr += 1ULL << 55; /* carry ptr[55] into ptr[59:56]. */
>> +return extract64(ptr, 56, 4);
>
> What's the carry-bit-55 logic for? The pseudocode
> AArch64.AllocationTagFromAddress
On 04/10/2019 11:37, David Gibson wrote:
> From: Alexey Kardashevskiy
>
> The ibm,client-architecture-support call is a way for the guest to
> negotiate capabilities with a hypervisor. It is implemented as:
> - the guest calls SLOF via client interface;
> - SLOF calls QEMU (H_CAS hypercall) with
On 11/25/19 2:37 PM, Philippe Mathieu-Daudé wrote:
> On 9/4/19 2:55 PM, Damien Hedde wrote:
>> Introduce clock objects: ClockIn and ClockOut.
>>
>> These objects may be used to distribute clocks from an object to several
>> other objects. Each ClockIn object contains the current state of the
>>
On 12/2/19 4:34 PM, Peter Maydell wrote:
> On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote:
>>
>> Add the connection between the slcr's output clocks and the uarts inputs.
>>
>> Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz
>> (the default frequency). This clock is
On 12/3/19 11:01 AM, Peter Maydell wrote:
>> +/* Return true if this address translation regime has two ranges. */
>> +static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx)
>> +{
>> +switch (mmu_idx) {
>> +case ARMMMUIdx_S12NSE0:
>> +case ARMMMUIdx_S12NSE1:
>> +case
On Tue, 3 Dec 2019 13:10:46 +
"Dr. David Alan Gilbert" wrote:
> * Paolo Bonzini (pbonz...@redhat.com) wrote:
> > On 03/12/19 14:02, Dr. David Alan Gilbert wrote:
> > >> It could be in fsdev/virtiofsd,
> > > fsdev is currently all 9p stuff, so that would seem very confusing.
> >
> > Move it
On 12/3/19 3:59 PM, Damien Hedde wrote:
On 12/2/19 4:34 PM, Peter Maydell wrote:
On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote:
Add the connection between the slcr's output clocks and the uarts inputs.
Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz
(the default
11.11.2019 19:02, Max Reitz wrote:
> Signed-off-by: Max Reitz
> ---
> tests/qemu-iotests/041 | 46 ++
> tests/qemu-iotests/041.out | 4 ++--
> 2 files changed, 48 insertions(+), 2 deletions(-)
>
> diff --git a/tests/qemu-iotests/041
Bad reply, the problem is with
"spapr: Render full FDT on ibm,client-architecture-support"
Sorry,
Laurent
On 03/12/2019 16:57, Laurent Vivier wrote:
> On 18/11/2019 11:53, Laurent Vivier wrote:
>> From: Alexey Kardashevskiy
>>
>> Since "spapr: Render full FDT on
On 12/2/19 2:42 PM, Peter Maydell wrote:
> On Wed, 4 Sep 2019 at 13:56, Damien Hedde wrote:
>>
>> Introduce clock objects: ClockIn and ClockOut.
>>
>> These objects may be used to distribute clocks from an object to several
>> other objects. Each ClockIn object contains the current state of
Ping
El mié., 6 nov. 2019 16:04, Esteban Bosse escribió:
> Hello!
>
> Some months ago I started to work trying to port the Beaglebone support
> from the old qemu-linaro fork to the new QEMU mainstream.
>
> During my work I found that the Beaglebone have an OMAP3 mpu this mpu has
> very strong
burak sarac writes:
> Hello All,
> Currently I am studying qemu and I want to figure out how I can use
> custom logic gates on user space emulation. I am searching very basic
> 'hello world' kind of tutorial or some resources to i.e. adding left
> or LOR : 1 | 0 = 1 but 0 | 1 = 0 to existing
On 11/25/19 2:30 PM, Philippe Mathieu-Daudé wrote:
> Nitpick: remove trailing dot in patch subject
>
> On 9/4/19 2:55 PM, Damien Hedde wrote:
>> Add functions to easily add input or output clocks to a device.
>> A clock objects is added as a child of the device.
>
> ?
>
>> The api is very
On Tue, 3 Dec 2019 at 16:06, Richard Henderson
wrote:
> On 12/3/19 1:42 PM, Peter Maydell wrote:
> > This reads a bit oddly, because (in the final version of the spec)
> > physical and logical tags are identical (AArch64.PhysicalTag()
> > just returns bits [59:56] of the vaddr).
>
> I missed that
On Tue, 3 Dec 2019 14:33:25 +0100
Christian Borntraeger wrote:
> On 03.12.19 14:28, Janosch Frank wrote:
> > We need to set the short psw indication bit in the reset psw, as it is
> > a short psw.
> >
> > fixes: 9629823290 ("pc-bios/s390-ccw: do a subsystem reset before running
> > the guest")
Wainer dos Santos Moschetta writes:
> Since commit cbe6d6365a48 the command `qemu -accel help` returns
> the list of accelerators enabled in the QEMU binary. This adds
> the list_accel() method which return that same list.
>
> Signed-off-by: Wainer dos Santos Moschetta
> ---
>
On 03/12/19 15:28, Kevin Wolf wrote:
>> * It's possible to argue against this and personally I'm not that
>> convinced by stubs for this scenario. But io_uring.o should be
>> consistent with how things work today with linux-aio.o. If you feel
>> strongly against having stubs then the linux-aio.o
Oh, to finish up on the replies...
On 12/3/19 1:42 PM, Peter Maydell wrote:
>> +ptr_tag = allocation_tag_from_addr(dirty_ptr);
>> +if (ptr_tag == 0) {
>> +ARMVAParameters p = aa64_va_parameters(env, dirty_ptr, stage1,
>> true);
>> +if (p.tcma) {
>> +return
On 18/11/2019 11:53, Laurent Vivier wrote:
> From: Alexey Kardashevskiy
>
> Since "spapr: Render full FDT on ibm,client-architecture-support" we build
> the entire flatten device tree (FDT) twice - at the reset time and
> when "ibm,client-architecture-support" (CAS) is called. The full FDT from
ping...
On 11/14/19 2:42 PM, Wainer dos Santos Moschetta wrote:
By default VM build test use qemu-img from system's PATH to
create the image disk. Due the lack of qemu-img on the system
or the desire to simply use a version built with QEMU, it would
be nice to allow one to set its path. So this patch
Wainer dos Santos Moschetta writes:
> This creates the 'accel' Python module to be the home for
> utilities that deal with accelerators. Also moved kvm_available()
> from __init__.py to this new module.
>
> Signed-off-by: Wainer dos Santos Moschetta
> ---
> python/qemu/__init__.py | 20
Wainer dos Santos Moschetta writes:
> This adds a method to check if the tcg accelerator is enabled
> in the QEMU binary.
>
> Signed-off-by: Wainer dos Santos Moschetta
Reviewed-by: Alex Bennée
So is this series going to be combined with another avocado series?
> ---
>
On Mon, 25 Nov 2019 19:57:39 -0500
Yan Zhao wrote:
> On Fri, Nov 15, 2019 at 05:06:25AM +0800, Alex Williamson wrote:
> > On Fri, 15 Nov 2019 00:26:07 +0530
> > Kirti Wankhede wrote:
> >
> > > On 11/14/2019 1:37 AM, Alex Williamson wrote:
> > > > On Thu, 14 Nov 2019 01:07:21 +0530
> > > >
If the redirected device has this capability, Windows guest may
place the device into D2 and expect it to wake when the device
becomes active, but this will never happen. For example, when
internal Bluetooth adapter is redirected, keyboards and mice
connected to it do not work. Current commit
Thomas Huth writes:
> It's much easier if we simply add the folder prefix and the exe suffix
> later via a substitution instead.
I guess it took too long for me to get around to this as I'm hit with a
merge conflict. Is there likely to be a re-base soon?
>
> Signed-off-by: Thomas Huth
> ---
11.11.2019 19:02, Max Reitz wrote:
> Signed-off-by: Max Reitz
> ---
> tests/qemu-iotests/041 | 235 +
> tests/qemu-iotests/041.out | 4 +-
> 2 files changed, 237 insertions(+), 2 deletions(-)
>
> diff --git a/tests/qemu-iotests/041
On 12/3/19 1:48 PM, Andrew Jeffery wrote:
On Tue, 3 Dec 2019, at 16:39, Philippe Mathieu-Daudé wrote:
On 12/3/19 5:14 AM, Andrew Jeffery wrote:
Prepare for SoCs such as the ASPEED AST2600 whose firmware configures
CNTFRQ to values significantly larger than the static 62.5MHz value
currently
Hi!
First, please, when sending more than one patch, create a cover-letter. Also,
summarize (in cover letter) what was changed since previous version.
29.11.2019 10:25, pannengy...@huawei.com wrote:
> From: PanNengyuan
Strange line. Check you git preferences. Such line appears (and make sense)
This series of patches addresses possible functional problem of USB
devices with 'remote wakeup' capability, redirected to Windows VM
(local redirection using libusb or spice redirection using usbredir).
Changes from v1: minor fixes per v1 review and checkpatch
Yuri Benditovich (2):
usb-host:
On Mon, 2 Dec 2019 at 14:06, Cleber Rosa wrote:
>
> RFC: QEMU Gating CI
> ===
>
> This RFC attempts to address most of the issues described in
> "Requirements/GatinCI"[1]. An also relevant write up is the "State of
> QEMU CI as we enter 4.0"[2].
>
> The general approach is one to
On 11/15/19 7:08 PM, Wainer dos Santos Moschetta wrote:
On commit abf0bf998dcb John Snow moved some code out of __init__.py
to machine.py. kvm_available() remained in though. So on patch 01
I continue his work by creating a home for that method (the new
'accel' module). Honestly I was unsure
If the redirected device has this capability, Windows guest may
place the device into D2 and expect it to wake when the device
becomes active, but this will never happen. For example, when
internal Bluetooth adapter is redirected, keyboards and mice
connected to it do not work. Current commit
On Tue, 3 Dec 2019 08:28:13 -0500
Janosch Frank wrote:
> We need to set the short psw indication bit in the reset psw, as it is
> a short psw.
>
> fixes: 9629823290 ("pc-bios/s390-ccw: do a subsystem reset before running the
> guest")
s/fixes: 9629823290/Fixes: 962982329029/
>
On 11/29/19 1:25 AM, pannengy...@huawei.com wrote:
From: PanNengyuan
The BDRVNBDState cleanup code is common in two places, add
nbd_free_bdrvstate_prop() function to do these cleanups (suggested by
Stefano Garzarella).
Signed-off-by: PanNengyuan
---
block/nbd.c | 23 +--
Hello Philippe,
On Tue, Dec 3, 2019 at 10:02 AM Philippe Mathieu-Daudé
wrote:
> On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> > Dear QEMU developers,
> >
> > Hereby I would like to contribute the following set of patches to QEMU
> > which add support for the Allwinner H3 System on Chip and the
Cleber Rosa writes:
> This acceptance test, validates that a full blown Linux guest can
> successfully boot in QEMU. In this specific case, the guest chosen is
> Fedora version 31.
>
> * x86_64, pc and q35 machine types, with and without kvm as an
>accellerator
>
> * aarch64 and virt
Wainer dos Santos Moschetta writes:
> Currently kvm_available() checks for the presence of kvm module
> and, if target and host arches don't mismatch. This patch adds
> an 3rd checking: if QEMU binary was compiled with kvm
> support.
>
> Signed-off-by: Wainer dos Santos Moschetta
It's just a memory leak, but it's a regression in 4.2.
Should we take it into 4.2?
29.11.2019 10:25, pannengy...@huawei.com wrote:
> From: PanNengyuan
>
> In currently implementation there will be a memory leak when
> nbd_client_connect() returns error status. Here is an easy way to
>
On Tue, 3 Dec 2019 08:28:11 -0500
Janosch Frank wrote:
> Up to now we only had an ioctl to reset vcpu data QEMU couldn't reach
> for the initial reset, and that was also called for the clear
> reset. To be architecture compliant, we also need to clear local
> interrupts on a normal reset.
>
>
On 03.12.19 14:28, Janosch Frank wrote:
> We need to set the short psw indication bit in the reset psw, as it is
> a short psw.
>
> fixes: 9629823290 ("pc-bios/s390-ccw: do a subsystem reset before running the
> guest")
> Signed-off-by: Janosch Frank
Acked-by: Christian Borntraeger
> ---
>
On 12/3/19 11:52 AM, Vladimir Sementsov-Ogievskiy wrote:
It's just a memory leak, but it's a regression in 4.2.
Should we take it into 4.2?
Sorry, I was on holiday and then jury service, so I missed any chance at
getting this into -rc3. The memory leak only happens on failure, and
you'd
Hello Frederic,
Thank you for your quick review comments!
I'll start working on v2 of the patches and include the changes you
suggested.
On Tue, Dec 3, 2019 at 10:33 AM KONRAD Frederic
wrote:
>
>
> Le 12/2/19 à 10:09 PM, Niek Linnenbank a écrit :
> > The Allwinner H3 System on Chip includes an
On 03/12/2019 20.24, Alex Bennée wrote:
>
> Thomas Huth writes:
>
>> It's much easier if we simply add the folder prefix and the exe suffix
>> later via a substitution instead.
>
> I guess it took too long for me to get around to this as I'm hit with a
> merge conflict. Is there likely to be a
On Tue, Dec 03, 2019 at 09:56:15AM +0100, Thomas Huth wrote:
> On 02/12/2019 22.00, Eduardo Habkost wrote:
> > On Mon, Dec 02, 2019 at 08:39:48AM +0100, Igor Mammedov wrote:
> >> On Fri, 29 Nov 2019 18:46:12 +0100
> >> Paolo Bonzini wrote:
> >>
> >>> On 29/11/19 13:16, Igor Mammedov wrote:
>
On 12/1/19 11:07 PM, Markus Armbruster wrote:
{
+Error *err = NULL;
I remember that some time ago, the best practice was to use "local_err",
what is the latest state of that?
Hundreds of local Error * variables are named @local_err, and hundreds
more are named @err.
For what it's
On 12/3/19 12:54 PM, Eric Blake wrote:
On 12/3/19 11:52 AM, Vladimir Sementsov-Ogievskiy wrote:
It's just a memory leak, but it's a regression in 4.2.
Should we take it into 4.2?
Sorry, I was on holiday and then jury service, so I missed any chance at
getting this into -rc3. The memory
On 03/12/2019 08:25, Thomas Huth wrote:
> On 03/12/2019 08.45, Philippe Mathieu-Daudé wrote:
>> On 12/3/19 8:29 AM, Thomas Huth wrote:
>>> It's been deprecated since QEMU v3.1. The 40p machine should be
>>> used nowadays instead.
>>>
>>> Signed-off-by: Thomas Huth
>>> ---
>>> .gitmodules
Include definitions for all of the bits in ID_MMFR3.
We already have a definition for ID_AA64MMFR1.PAN.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 29 +
1 file changed, 29 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index
In target/arm we will shortly have "too many" mmu_idx.
The current minimum barrier is caused by the way in which
tlb_flush_page_by_mmuidx is coded.
We can remove this limitation by allocating memory for
consumption by the worker. Let us assume that this is
the unlikely case, as will be the case
To implement PAN, we will want to swap, for short periods
of time, to a different privileged mmu_idx. In addition,
we cannot do this with flushing alone, because the AT*
instructions have both PAN and PAN-less versions.
Add the ARMMMUIdx*_PAN constants where necessary next to
the corresponding
The PAN bit is preserved, or set as per SCTLR_ELx.SPAN,
plus several other conditions listed in the ARM ARM.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 42 +++---
1 file changed, 39 insertions(+), 3 deletions(-)
diff --git
Hi Philippe,
Thanks for your very quick response!
I remember I have seen this error before while working on the patches, in
particular
on the SMP part. I'll try to reproduce this error with the 4.20 sunxi
kernel you used and debug it.
Could it be related to the change I made in patch 0006 for
On 11/20/19 7:39 AM, Cornelia Huck wrote:
> On Fri, 15 Nov 2019 04:34:36 +0100
> Eric Farman wrote:
>
>> Make it easier to add new ones in the future.
>>
>> Signed-off-by: Eric Farman
>> ---
>> hw/vfio/ccw.c | 55 ---
>> 1 file changed, 39
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
fifth release candidate for the QEMU 4.2 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-4.2.0-rc4.tar.xz
To the best of my knowledge, -blockdev can fully replace -drive if=none.
Replacing other interface types takes more than just -blockdev, because
they additionally instruct the board code to create a block frontend.
-blockdev is *only* about backends, so something else needs to replace
the frontend
Any insight as to why OS vendors (RHEL and Ubuntu in particular)
aren't supporting blockdev-snapshot?
- RHEL claims no support for Qemu-based snapshots in any flavor
- Ubuntu hasn't enabled blockdev-snapshot in it's 19.10 release
-craig
Since v8.0, the CPSR_RESERVED bits have been allocated.
We are not yet implementing ARMv8.4-DIT; retain CPSR_RESERVED,
since that overlaps with our current hack for AA32 single step.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 8 ++--
1 file changed, 6 insertions(+), 2
Based-on: <20191203022937.1474-1-richard.hender...@linaro.org>
("target/arm: Implement ARMv8.1-VHE")
At least the PAN portion is supported in the Linux kernel,
and thus easily tested. The ats1e1 extension is closely
related, reusing the same mmu_idx to implement.
r~
Richard Henderson (11):
If we have a PAN-enforcing mmu_idx, set prot == 0 if user_rw != 0.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 13 +
target/arm/helper.c| 3 +++
2 files changed, 16 insertions(+)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index
Use a common predicate for querying stage1-ness.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 11 +++
target/arm/helper.c| 8 +++-
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index
On Mon, 2 Dec 2019 17:40:07 +0100
Cornelia Huck wrote:
> On Sat, 30 Nov 2019 20:42:39 +0100
> Markus Armbruster wrote:
>
> > Cc: Halil Pasic
> > Cc: Cornelia Huck
> > Cc: Christian Borntraeger
> > Signed-off-by: Markus Armbruster
> > ---
> > hw/intc/s390_flic_kvm.c | 10 --
> > 1
Examine the PAN bit for EL1, EL2, and Secure EL1 to
determine if it applies.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 512be5c644..6c65dd799e 100644
---
This includes enablement of ARMv8.1-PAN.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 4
target/arm/cpu64.c | 5 +
2 files changed, 9 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f3360dbb98..3b0c466137 100644
--- a/target/arm/cpu.c
+++
For aarch64, there's a dedicated msr (imm, reg) insn.
For aarch32, this is done via msr to cpsr; and writes
from el0 are ignored.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 ++
target/arm/helper.c| 22 ++
target/arm/translate-a64.c | 14
This is a minor enhancement over ARMv8.1-PAN.
The *_PAN mmu_idx are used with the existing do_ats_write.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 50 +++--
1 file changed, 44 insertions(+), 6 deletions(-)
diff --git
Add definitions for all of the fields, up to ARMv8.5.
Convert the existing RESERVED register to a full register.
Query KVM for the value of the register for the host.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 17 +
target/arm/helper.c | 4 ++--
We need only override the current condition under which
TBFLAG_A64.UNPRIV is set.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 41 +
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
Hello Philippe,
Thanks for your quick review comments!
I'll start working on a v2 of the patches and include the changes you
suggested.
Regards,
Niek
On Tue, Dec 3, 2019 at 10:18 AM Philippe Mathieu-Daudé
wrote:
> On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> > The Xunlong Orange Pi PC is an
Public bug reported:
While running the acceptance tests on s390x, the arm tests under
qemu/tests/acceptance/boot_linux_console.py will timeout, except the
test using u-boot. All the arm tests run without problems on x86 and
ppc.
This test boots the kernel and wait for a kernel panic to make sure
+jfreimann, +mst
On Sat, Nov 30, 2019 at 11:10:19AM +, Peter Maydell wrote:
> On Fri, 29 Nov 2019 at 20:05, Eduardo Habkost wrote:
> > So, to summarize the current issues:
> >
> > 1) realize triggers a plug operation implicitly.
> > 2) unplug triggers unrealize implicitly.
> >
> > Do you
On 11/30/19 1:42 PM, Markus Armbruster wrote:
Signed-off-by: Markus Armbruster
---
tests/test-blockjob.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
Reviewed-by: Eric Blake
diff --git a/tests/test-blockjob.c b/tests/test-blockjob.c
index e670a20617..4eeb184caf 100644
---
On 12/2/19 10:25 PM, Philippe Mathieu-Daudé wrote:
> On 12/3/19 3:29 AM, Richard Henderson wrote:
>> No functional change, but unify code sequences.
>>
>> Reviewed-by: Alex Bennée
>> Signed-off-by: Richard Henderson
>
> Easier to review in 2 patches: vae1_tlbmask first, then vmalle1_tlbmask.
On 11/29/19 3:59 AM, Markus Armbruster wrote:
Generated .h need to be generated before compiling any .c using them.
To know which .h a .c uses, we need to compile it.
Since commit 4115852bb0 "build: do not sprinkle around
GENERATED_HEADERS dependencies", we break this circular dependency the
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 9399253b4c..03377084e3 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -674,6 +674,10 @@ static void aarch64_max_initfn(Object
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 6 ++
target/arm/helper.c| 21 +
target/arm/translate-a64.c | 14 ++
3 files changed, 41 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index cdf6caf869..dd284ba5c7
Add function pointer apic_id_from_topo_ids in PCMachineState.
Initialize with correct handler based on the mode selected.
Also rename the handler apicid_from_topo_ids to x86_apicid_from_topo_ids
for consistency. x86_apicid_from_topo_ids will be the default handler.
Signed-off-by: Babu Moger
Add function pointers in PCMachineState to handle apic id specific
functionalities. This will be used to initialize with correct handlers based on
the cpu model selected.
x86_apicid_from_cpu_idx will be default handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |5 -
Introduce last level cache id(llc_id) in x86CPU topology. This information is
required to build the topology in EPIC mode.
Signed-off-by: Babu Moger
---
hw/core/machine-hmp-cmds.c |3 +++
hw/core/machine.c | 13 +
hw/i386/pc.c | 10 ++
Now that we have all the parameters in X86CPUTopoInfo, we can just pass the
structure to calculate the offsets and width.
Signed-off-by: Babu Moger
---
include/hw/i386/topology.h | 64 ++--
target/i386/cpu.c | 23
2 files
This is an effort to re-arrange few data structure for better readability.
Add X86CPUTopoInfo which will have all the topology informations required
to build the cpu topology. There is no functional changes.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 40
Based-on: <20191203225333.17055-1-richard.hender...@linaro.org>
("target/arm: Implement ARMv8.1-PAN + ARMv8.2-ATS1E1")
This was relatively easy to do, and related to the VHE
and PAN patch sets. It's also already supported by the
Linux kernel and thus easily tested.
r~
Richard Henderson (4):
These functions add support for building EPYC mode topology given the smp
details like numa nodes, cores, threads and sockets.
The new apic id decoding is mostly similar to current apic id decoding
except that it adds a new field llc_id when numa configured. Removes all
the hardcoded values.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e87487bae3..0eaedeb848 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4456,7 +4456,7 @@ void
Introduce following handlers for new epyc mode.
x86_apicid_from_cpu_idx_epyc: Generate apicid from cpu index.
x86_topo_ids_from_apicid_epyc: Generate topo ids from apic id.
x86_apicid_from_topo_ids_epyc: Generate apicid from topo ids.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |
This series fixes APIC ID encoding problems on AMD EPYC CPUs.
https://bugzilla.redhat.com/show_bug.cgi?id=1728166
Currently, the APIC ID is decoded based on the sequence
sockets->dies->cores->threads. This works for most standard AMD and other
vendors' configurations, but this decoding sequence
Rename few data structures related to X86 topology. X86CPUTopoIDs will
have individual arch ids. Next patch introduces X86CPUTopoInfo which will
have all topology information(like cores, threads etc..).
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/i386/pc.c |
Use the new functions from topology.h and delete the unused code. Given the
sockets, nodes, cores and threads, the new functions generate apic id for EPYC
mode. Removes all the hardcoded values.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 162
Add function pointer topo_ids_from_apicid in PCMachineState.
Initialize with correct handler based on mode selected.
x86_apicid_from_cpu_idx will be the default handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 13 +++--
include/hw/i386/pc.h |2 ++
2 files changed, 9
Since the topology routines have changed, update
the unit tests to use the new APIs.
Signed-off-by: Babu Moger
---
tests/test-x86-cpuid.c | 115
1 file changed, 68 insertions(+), 47 deletions(-)
diff --git a/tests/test-x86-cpuid.c
Add a new function init_apicid_fn in MachineClass to initialize the mode
specific handlers to decode the apic ids.
Signed-off-by: Babu Moger
---
include/hw/boards.h |1 +
vl.c|3 +++
2 files changed, 4 insertions(+)
diff --git a/include/hw/boards.h b/include/hw/boards.h
101 - 200 of 218 matches
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