在 2024/1/22 下午3:12, maobibo 写道:
On 2024/1/22 下午2:09, Song Gao wrote:
The kernel had already support LSX and LASX [1],
but QEMU is disable LSX/LASX for kvm. This patch adds
kvm_check_cpucfg to check CPUCFG2.
[1]:
Hi Eric,
>-Original Message-
>From: Duan, Zhenzhong
>Subject: RE: [RFC 4/7] virtio-iommu: Implement PCIIOMMUOps
>set_host_resv_regions
>
>
>
>>-Original Message-
>>From: Eric Auger
>>Subject: Re: [RFC 4/7] virtio-iommu: Implement PCIIOMMUOps
>>set_host_resv_regions
>>
>>Hi
On Mon, Jan 22, 2024 at 12:17:24AM +0100, Philippe Mathieu-Daudé wrote:
> > @@ -560,7 +569,7 @@ static const VMStateDescription
> > vmstate_designware_pcie_viewport = {
> > .fields = (const VMStateField[]) {
> > VMSTATE_UINT64(base, DesignwarePCIEViewport),
> >
On 2024/1/22 下午2:09, Song Gao wrote:
The kernel had already support LSX and LASX [1],
but QEMU is disable LSX/LASX for kvm. This patch adds
kvm_check_cpucfg to check CPUCFG2.
[1]:
https://lore.kernel.org/all/cabgobfzhrf7e_7jk4uprmsyxty3eiuuywhc35jqncnl9s-z...@mail.gmail.com/
Signed-off-by:
From: Peter Xu
The current article is not extremely easy to follow, and may contain too
much information for someone looking for solutions on VMSD compatibility
issues. Meanwhile, VMSD versioning is not discussed.
I'm not yet sure whether we should just obsolete VMSD versioning; it's
still
On Tue, Jan 9, 2024 at 8:32 PM Alexey Baturo wrote:
>
> From: Alexey Baturo
>
> Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 8
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/cpu_cfg.h | 3 +++
> target/riscv/csr.c
On Tue, Jan 9, 2024 at 8:31 PM Alexey Baturo wrote:
>
> From: Alexey Baturo
>
> Signed-off-by: Alexey Baturo
>
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h| 3 +++
> target/riscv/cpu_helper.c | 3 +++
> target/riscv/translate.c
On Tue, Jan 9, 2024 at 9:33 PM Alexey Baturo wrote:
>
> From: Alexey Baturo
>
> Signed-off-by: Alexey Baturo
>
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate.c | 22 --
> target/riscv/vector_helper.c | 13
On Tue, Jan 9, 2024 at 8:31 PM Alexey Baturo wrote:
>
> From: Alexey Baturo
>
> Signed-off-by: Alexey Baturo
> ---
> target/riscv/cpu.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d8de1f1890..44ebd80aba 100644
> ---
On Tue, Jan 9, 2024 at 8:30 PM Alexey Baturo wrote:
>
> From: Alexey Baturo
>
> Zjpm v0.8 is almost frozen and it's much simplier compared to the existing
> one:
> The newer version doesn't allow to specify custom mask or base for masking.
> Instead it allows only certain options for masking
On Tue, Jan 9, 2024 at 8:31 PM Alexey Baturo wrote:
>
> From: Alexey Baturo
>
> Hi,
>
Do you mind including a pointer to the exact spec (a Github link with
the SHA or tag is great) that you are targeting? We are having issues
with a different spec, so it will be helpful in future to know
On Tue, Jan 2, 2024 at 7:22 PM Nati Rapaport wrote:
>
> Hello,
>
> I’m going to add some custom CSRs (Control & Status Registers) to a new RiscV
> core in qemu.
>
> Could you please help me understanding if there is any method to do it?
Have a look at decode_opc() in target/riscv/translate.c.
This adds PCI device's real bus and devfn to API get_address_space(),
for vIOMMU which also wants real BDF, i.e., virtio-iommu.
Signed-off-by: Zhenzhong Duan
---
include/hw/pci/pci.h | 11 ---
hw/alpha/typhoon.c | 3 ++-
hw/arm/smmu-common.c | 3 ++-
hw/i386/amd_iommu.c
Currently virtio-iommu doesn't work well if there are multiple devices
in same iommu group. In below example config, guest virtio-iommu driver
can successfully probe first device but fail on others. Only one device
under the bridge can work normally.
-device virtio-iommu \
-device
PATCH1 fixes a potential issue with vfio devices when reboot to a
different OS which set bus number differently from previous OS.
I didn't reproduce the issue in reality, but it's still possible
in theory.
PATCH2 is a prerequisite of of PATCH3.
PATCH3 make virtio-iommu support PCI device
IOMMUPciBus pointer cache is indexed by bus number, bus number
may not always be a fixed value, i.e., guest reboot to different
kernel which set bus number with different algorithm.
This could lead to endpoint binding to wrong iommu MR in
virtio_iommu_get_endpoint(), then vfio device setup wrong
From: Taylor Simpson
These functions are no longer used after making the generators
object oriented.
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20231210220712.491494-10-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 51
From: Taylor Simpson
This is the only remaining use of the is_written function. We will
remove it in the subsequent commit.
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20231210220712.491494-9-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20231210220712.491494-6-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/gen_idef_parser_funcs.py | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff
From: Taylor Simpson
The generators are generally a bunch of Python if-then-else
statements based on the regtype and regid. Encapsulate regtype/regid
into a class hierarchy. Clients lookup the register and invoke
methods.
This has several advantages for making the code easier to read,
This is intended to address a coverity finding: CID 1527408.
Signed-off-by: Brian Cain
Reviewed-by: Matheus Tavares Bernardino
Message-Id: <20240114234453.4114587-1-bc...@quicinc.com>
---
target/hexagon/mmvec/decode_ext_mmvec.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff
From: Taylor Simpson
Section 10.3 of the Hexagon V73 Programmer's Reference Manual
A duplex is encoded as a 32-bit instruction with bits [15:14] set to 00.
The sub-instructions that comprise a duplex are encoded as 13-bit fields
in the duplex.
Create a decoder for each subinstruction class (a,
This update includes support for privileged instructions.
Signed-off-by: Brian Cain
Reviewed-by: Matheus Tavares Bernardino
Tested-by: Matheus Tavares Bernardino
Message-Id: <20240114232354.4109231-1-bc...@quicinc.com>
---
tests/docker/dockerfiles/debian-hexagon-cross.docker | 4 ++--
1 file
From: Taylor Simpson
Adding -Werror=shadow=compatible-local causes Hexagon not to build
when idef-parser is off. The "label" variable in CHECK_NOSHUF_PRED
shadows a variable in the surrounding code.
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Reviewed-by: Philippe Mathieu-Daudé
From: Taylor Simpson
The Decodetree Specification can be found here
https://www.qemu.org/docs/master/devel/decodetree.html
Covers all 32-bit instructions, including HVX
We generate separate decoders for each instruction class. The reason
will be more apparent in the next patch in this series.
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20231210220712.491494-5-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/gen_helper_funcs.py | 370 +
target/hexagon/hex_common.py | 48 +++-
2
From: Taylor Simpson
Now that we are using QEMU decodetree.py, remove the old decoder
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240115221443.365287-4-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/decode.c | 344
From: Taylor Simpson
Currently, the register number (MuN) for modifier registers is the
modifier register number rather than the index into hex_gpr. This
patch changes MuN to the hex_gpr index, which is consistent with
the handling of control registers.
Note that HELPER(fcircadd) needs the CS
From: Taylor Simpson
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20231210220712.491494-4-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/gen_helper_protos.py | 149 ++--
target/hexagon/hex_common.py| 7 --
2
From: Taylor Simpson
Reviewed-by: Brian Cain
Signed-off-by: Taylor Simpson
Message-Id: <20231210220712.491494-7-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
target/hexagon/gen_op_regs.py | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
From: Taylor Simpson
This patch conflicts with
https://lists.gnu.org/archive/html/qemu-devel/2023-11/msg00729.html
If that series goes in first, we'll rework this patch and vice versa.
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id:
The following changes since commit 3f2a357b95845ea0bf7463eff6661e43b97d1afc:
Merge tag 'hw-cpus-20240119' of https://github.com/philmd/qemu into staging
(2024-01-19 11:39:38 +)
are available in the Git repository at:
https://github.com/quic/qemu tags/pull-hex-20240121
for you to fetch
The kernel had already support LSX and LASX [1],
but QEMU is disable LSX/LASX for kvm. This patch adds
kvm_check_cpucfg to check CPUCFG2.
[1]:
https://lore.kernel.org/all/cabgobfzhrf7e_7jk4uprmsyxty3eiuuywhc35jqncnl9s-z...@mail.gmail.com/
Signed-off-by: Song Gao
---
On Thu, Dec 21, 2023 at 4:38 PM Ethan Chen wrote:
>
> On Mon, Dec 18, 2023 at 02:18:58PM +1000, Alistair Francis wrote:
> > On Wed, Nov 22, 2023 at 3:36 PM Ethan Chen via
> > wrote:
> > >
> > > This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
> > > The specification url:
>-Original Message-
>From: Jason Wang
>Subject: Re: [PATCH rfcv1 00/23] intel_iommu: Enable stage-1 translation
>
>On Mon, Jan 15, 2024 at 6:39 PM Zhenzhong Duan
> wrote:
>>
>> Hi,
>>
>> This series enables stage-1 translation support in intel iommu which
>> we called "modern" mode. In
On Sat, Jan 13, 2024 at 8:04 AM Richard Henderson
wrote:
>
> Reported-by: Vineet Gupta
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> linux-user/riscv/vdso-32.so | Bin 2900 -> 2900 bytes
> linux-user/riscv/vdso-64.so | Bin 3856 -> 3856 bytes
>
On Fri, Jan 19, 2024 at 9:22 PM Rob Bradford wrote:
>
> These extensions represent the atomic operations from A (Zaamo) and the
> Load-Reserved/Store-Conditional operations from A (Zalrsc)
>
> Signed-off-by: Rob Bradford
> Reviewed-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 5
On Fri, Jan 12, 2024 at 11:34 PM Rob Bradford wrote:
>
> On Fri, 2024-01-12 at 13:52 +1000, Alistair Francis wrote:
> > On Thu, Jan 11, 2024 at 5:20 AM Daniel Henrique Barboza
> > wrote:
> > >
> > > Himanshu,
> > >
> > > We spoke offline but let's make everyone aware:
> > >
> > > - 'sdtrig'
On Thu, Jan 18, 2024 at 12:25 AM Himanshu Chauhan
wrote:
>
> The debug trigger (sdtrig) capability is controlled using the debug property.
> The sdtrig is an ISA extension and should be treated so. The sdtrig extension
> may or may not be implemented in a system. Therefore, it must raise an
Hello,
I'm a QEMU user with PowerPc target architecture.
I have some personal modifications related to tb jmp cache and chaining
logic to improve the performance of a specific guest code. To verify the
safety, I have to guarantee that the page table on RAM does not change
after initialization. Do
On Tue, Dec 19, 2023 at 10:34 PM Alvin Chang via wrote:
>
> The debug Sdtrig extension defines an CSR "mcontext". This commit
> implements its predicate and read/write operations into CSR table.
> Its value is reset as 0 when the trigger module is reset.
>
> Signed-off-by: Alvin Chang
On Wed, Jan 10, 2024 at 8:27 PM Conor Dooley wrote:
>
> From: Conor Dooley
>
> Making it a series to keep the standalone change to riscv_isa_string()
> that Drew reported separate.
>
> Changes in v3:
> - g_free() isa_extensions too
> - use misa_mxl_max rather than the compile target for the base
On Wed, Jan 10, 2024 at 8:28 PM Conor Dooley wrote:
>
> From: Conor Dooley
>
> A few months ago I submitted a patch to various lists, deprecating
> "riscv,isa" with a lengthy commit message [0] that is now commit
> aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux
> kernel
On Wed, Jan 10, 2024 at 9:34 PM Conor Dooley wrote:
>
> From: Conor Dooley
>
> A cpu may not have the same xlen as the compile time target, and
> misa_mxl_max is the source of truth for what the hart supports.
>
> Reported-by: Andrew Jones
> Link:
>
On Tue, Jan 9, 2024 at 10:29 AM Atish Patra wrote:
>
> Privilege mode filtering can also be emulated for cycle/instret by
> tracking host_ticks/icount during each privilege mode switch. This
> patch implements that for both cycle/instret and mhpmcounters. The
> first one requires Smcntrpmf while
On Tue, Jan 9, 2024 at 10:29 AM Atish Patra wrote:
>
> From: Kaiwen Xue
>
> QEMU only calculates dummy cycles and instructions, so there is no
> actual means to stop the icount in QEMU. Hence this patch merely adds
> the functionality of accessing the cfg registers, and cause no actual
> effects
On Tue, Jan 9, 2024 at 12:05 PM Atish Patra wrote:
>
> From: Kaiwen Xue
>
> This adds the definitions for ISA extension smcntrpmf.
>
> Signed-off-by: Kaiwen Xue
> Reviewed-by: Daniel Henrique Barboza
> Signed-off-by: Atish Patra
Acked-by: Alistair Francis
Alistair
> ---
>
On Tue, Jan 9, 2024 at 11:04 AM Atish Patra wrote:
>
> From: Kaiwen Xue
>
> This adds the properties for ISA extension smcntrpmf. Patches
> implementing it will follow.
>
> Signed-off-by: Atish Patra
> Signed-off-by: Kaiwen Xue
Reviewed-by: Alistair Francis
Alistair
> ---
>
On Fri, Jan 5, 2024 at 3:44 PM Heinrich Schuchardt
wrote:
>
> On 1/5/24 06:24, Alistair Francis wrote:
> > On Fri, Dec 29, 2023 at 10:48 PM Heinrich Schuchardt
> > wrote:
> >>
> >> For RISC-V the SMBIOS standard requires specific values of the processor
> >> family value depending on the bitness
On Fri, Dec 29, 2023 at 10:48 PM Heinrich Schuchardt
wrote:
>
> For RISC-V the SMBIOS standard requires specific values of the processor
> family value depending on the bitness of the CPU.
>
> Add a processor-family option for SMBIOS table 4.
>
> The value of processor-family may exceed 255 and
This patch allows the qemu ufs to raise an interrupt on
the DME_SET (PA_PWRMODE) command.
Signed-off-by: Jeuk Kim
---
hw/ufs/ufs.c| 15 ++-
include/block/ufs.h | 65 +
2 files changed, 79 insertions(+), 1 deletion(-)
diff --git
On Sat, Jan 13, 2024 at 8:31 PM Arnaud Minier
wrote:
>
> Signed-off-by: Arnaud Minier
> Signed-off-by: Inès Varhol
Acked-by: Alistair Francis
Alistair
> ---
> hw/misc/stm32l4x5_rcc.c | 154 ++
> hw/misc/trace-events | 5 +
>
On Sat, Jan 13, 2024 at 8:30 PM Arnaud Minier
wrote:
>
> Signed-off-by: Arnaud Minier
> Signed-off-by: Inès Varhol
> ---
> MAINTAINERS | 5 +-
> docs/system/arm/b-l475e-iot01a.rst| 2 +-
> hw/arm/Kconfig| 1 +
>
On Mon, Jan 15, 2024 at 6:39 PM Zhenzhong Duan wrote:
>
> Hi,
>
> This series enables stage-1 translation support in intel iommu which
> we called "modern" mode. In this mode, we don't do shadowing of
> guest page table for passthrough device but pass stage-1 page table
> to host side to
The command line options `-ctrl-grab` and `-alt-grab` have been removed
in QEMU 7.1. Instead, use the `-display sdl,grab-mod=` option
to specify the grab modifiers.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2103
Signed-off-by: Yihuan Pan
---
docs/system/keys.rst.inc | 11
On Sat, Jan 20, 2024 at 6:42 PM Michael Tokarev wrote:
>
> 02.01.2024 06:29, Jason Wang :
> > When HASH_REPORT is negotiated, the guest_hdr_len might be larger than
> > the size of the mergeable rx buffer header. Using
> > virtio_net_hdr_mrg_rxbuf during the header swap might lead a stack
> >
On Thu, Jan 18, 2024 at 5:10 PM wrote:
>
> From: Peter Xu
>
> Due to my own limitation on bandwidth, I noticed that unfortunately I won't
> have time to review VT-d patches at least in the near future. Meanwhile I
> expect a lot of possibilities could actually happen in this area in the
> near
On Tue, Jan 9, 2024 at 3:40 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This is the second version of a buried patch series:
>
> "[PATCH for-9.0 0/6] riscv: rv32i,rv32e,rv64i and rv64e CPUs"
>
> This version shrank to 2 patches since most of the prep work was already
> done by the RVA22 profile
On Wed, Jan 17, 2024 at 7:41 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> In this v3 the most significant change is with vext_get_vlmax() from
> cpu.h. The logic used in this function is also used in at least two
> other places, trans_vrgather_vi() and trans_vrgather_vx(), and we need
> to make
On Tue, Jan 9, 2024 at 2:19 AM Daniel Henrique Barboza
wrote:
>
> A bare bones 32 bit RVI CPU, rv32i, will make users lives easier when a
> full customized 32 bit CPU is desired, and users won't need to disable
> defaults by hand as they would with the rv32 CPU. [1] has an example of
> a
On Tue, Jan 9, 2024 at 3:32 AM Daniel Henrique Barboza
wrote:
>
> Next patch will add more bare CPUs. Their cpu_init() functions would be
> glorified copy/pastes of rv64i_bare_cpu_init(), differing only by a
> riscv_cpu_set_misa() call.
>
> Add a new .instance_init for the TYPE_RISCV_BARE_CPU typ
On Mon, Jan 15, 2024 at 2:36 PM Bin Meng wrote:
>
> At present we expect struct arm_boot_info::get_dtb() to return the
> device tree pointer as well as the device tree size. However, this
> is not necessary as we can get the device tree size via the device
> tree header directly. Change get_dtb()
On Wed, Jan 17, 2024 at 7:03 AM Daniel Henrique Barboza
wrote:
>
> There is no need to keep both 'vlen' and 'vlenb'. All existing code
> that requires 'vlen' is retrieving it via 'vlenb << 3'.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair
On Wed, Jan 17, 2024 at 7:02 AM Daniel Henrique Barboza
wrote:
>
> Use the helper instead of calculating vlmax by hand.
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 6 ++
> 1 file changed, 2
On Wed, Jan 17, 2024 at 7:02 AM Daniel Henrique Barboza
wrote:
>
> We'll re-use the logic froim vext_get_vlmax() in 2 other occurrences in
> the next patch, but first we need to make it independent of both 'cpu'
> and 'vtype'. To do that, add 'vlenb', 'vsew' and 'lmul' as parameters
> instead.
>
On Wed, Jan 17, 2024 at 7:02 AM Daniel Henrique Barboza
wrote:
>
> Rename the existing 'sew' variable to 'vsew' for extra clarity.
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 11 +--
> 1 file changed, 9
On Wed, Jan 17, 2024 at 7:02 AM Daniel Henrique Barboza
wrote:
>
> Calculate the maximum vector size possible, 'max_sz', which is the size
> in bytes 'vlenb' multiplied by the max value of LMUL (LMUL = 8, when
> s->lmul = 3).
>
> 'max_sz' is then shifted right by 'scale', expressed as '3 -
On Wed, Jan 17, 2024 at 7:02 AM Daniel Henrique Barboza
wrote:
>
> Use the new 'vlenb' CPU config to validate fractional LMUL. The original
> comparison is done with 'vlen' and 'sew', both in bits. Adjust the shift
> to use vlenb.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Richard
On Wed, Jan 17, 2024 at 8:18 AM Daniel Henrique Barboza
wrote:
>
> Use 'cpu->cfg.vlenb' instead of 'cpu->cfg.vlen >> 3'.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/vector_helper.c | 18
On Wed, Jan 17, 2024 at 7:01 AM Daniel Henrique Barboza
wrote:
>
> Use s->cfg_ptr->vlenb instead of s->cfg_ptr->vlen / 8.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rvvk.c.inc | 16
On Wed, Jan 17, 2024 at 7:00 AM Daniel Henrique Barboza
wrote:
>
> Use s->cfg_ptr->vlenb instead of "s->cfg_ptr->vlen / 8" and
> "s->cfg_ptr->vlen >> 3".
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
>
On Wed, Jan 17, 2024 at 8:17 AM Daniel Henrique Barboza
wrote:
>
> Use ctx->cfg_ptr->vlenb instead of ctx->cfg_ptr->vlen / 8.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
>
On Wed, Jan 17, 2024 at 7:00 AM Daniel Henrique Barboza
wrote:
>
> As a bonus, we're being more idiomatic using cpu->cfg.vlenb when
> reading CSR_VLENB.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
>
On Wed, Jan 17, 2024 at 7:00 AM Daniel Henrique Barboza
wrote:
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/gdbstub.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git
On Tue, Jan 9, 2024 at 12:54 PM Jonathan Cameron
wrote:
>
> On Fri, 22 Dec 2023 18:00:50 +0900
> Hyeonggon Yoo <42.hye...@gmail.com> wrote:
>
> > The spec states that reads/writes should have no effect and a part of
> > commands should be ignored when the media is disabled, not when the
> >
On Wed, Jan 17, 2024 at 7:00 AM Daniel Henrique Barboza
wrote:
>
> Our usage of 'vlenb' is overwhelming superior than the use of 'vlen'.
> We're using 'vlenb' most of the time, having to do 'vlen >> 3' or
> 'vlen / 8' in every instance.
>
> In hindsight we would be better if the 'vlenb' property
Hi, Peter,
On Fri, Jan 19, 2024 at 04:35:07PM +, Peter Maydell wrote:
> I wrote this ages ago and recently picked it back up because of a
> recent PCI related reset ordering problem noted by Peter Xu. I'm not
> sure if this patchset is necessary as a part of fixing that ordering
> problem
On 1/18/24 20:07, Igor Mammedov wrote:
On Thu, 18 Jan 2024 14:48:50 +0800
Kai wrote:
On 1/18/24 01:31, Peter Maydell wrote:
(cc'd the people listed for this file in MAINTAINERS)
On Tue, 9 Jan 2024 at 13:53, Kai Kang wrote:
When this section of source codes were added via commit:
*
Hi Shlomo,
On 21/1/24 17:47, Shlomo Pongratz wrote:
From: Shlomo Pongratz
Hanlde wrap around when calculating the viewport size
caused by the fact that perior to version 460A the limit variable
was 32bit quantity and not 64 bits quantity.
In the i.MX 6Dual/6Quad
On 1/3/24 10:44 AM, Gerd Hoffmann wrote:
> On Wed, Jan 03, 2024 at 12:44:39PM +, Daniel P. Berrangé wrote:
>> On Tue, Nov 28, 2023 at 09:36:47AM -0500, Cole Robinson wrote:
>>> binutils 2.39 shows some warnings when building pvh.img
>>>
>>> /usr/bin/ld: warning: pvh.o: missing .note.GNU-stack
When tcg_out_qemu_st_{index,direct} were merged, the direct case for
MO_64 was omitted, causing qemu_st_i64 to be encoded as 0x due
to underflow when adding h.base and h.index.
Fixes: 1df6d611bdc2("tcg/arm: Introduce HostAddress")
Signed-off-by: Joseph Burt
---
tcg/arm/tcg-target.c.inc
From: Shlomo Pongratz
Hanlde wrap around when calculating the viewport size
caused by the fact that perior to version 460A the limit variable
was 32bit quantity and not 64 bits quantity.
In the i.MX 6Dual/6Quad Applications Processor Reference Manual
document on which the
On 19.01.24 12:24, Alex Bennée wrote:
> Peter Maydell writes:
>
>> Convert the musicpal key input device to use
>> qemu_add_kbd_event_handler(). This lets us simplify it because we no
>> longer need to track whether we're in the middle of a PS/2 multibyte
>> key sequence.
>>
>> In the conversion
On 2024/01/18 20:38, Alex Bennée wrote:
Akihiko Odaki writes:
On 2024/01/16 19:48, Alex Bennée wrote:
We can only request a list of registers once the vCPU has been
initialised so the user needs to use either call the get function on
vCPU initialisation or during the translation phase.
We
On 11/01/2024 10:29, Mark Cave-Ayland wrote:
This series introduces a new nubus-virtio-mmio device which can be plugged into
the q800 machine to enable a 68k Classic MacOS guest to access virtio devices
such as virtio-9p-device (host filesharing), virtio-gpu (extended framebuffer
support) and
On 20/01/2024 13:09, Michael Tokarev wrote:
12.01.2024 16:15, Mark Cave-Ayland:
This series contains fixes for the esp-pci device (am53c974 or dc390) for a
few issues spotted whilst testing the previous ESP series.
Patches 1-3 are fixes for issues found by Helge/Guenter whilst testing the
On Fri, Jan 19, 2024 at 04:35:07PM +, Peter Maydell wrote:
> This patchset switches the handful of bus types that implement a
> reset method over to using the 3-phase-reset APIs, and then removes
> the transitional infrastructure from the core bus class that was
> supporting the ability to
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