On Tue, Aug 02, 2022 at 04:33:05PM -0700, Atish Patra wrote:
> Qemu virt machine can support few cache events and cycle/instret counters.
> It also supports counter overflow for these events.
>
> Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
> capabilities. There are some
On Wed, Aug 17, 2022 at 03:36:35PM +0800, Weiwei Li wrote:
> - modify check for mcounteren to work in all less-privilege mode
> - modify check for scounteren to work only when S mode is enabled
> - distinguish the exception type raised by check for scounteren between U
> and VU mode
>
> Signed-off
On Tue, Feb 14, 2023 at 09:13:28AM +0530, Sunil V L wrote:
> On Mon, Feb 13, 2023 at 03:48:04PM -0300, Daniel Henrique Barboza wrote:
> > Sunil,
> >
> > This patch is a bit confusing to me. You're using functions that doesn't
> > exist
> > in the code base yet (build_madt and build_rhct) because
ample.
> /* create device tree */
> create_fdt(s, memmap);
>
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index b3d26135c0..6c7885bf89 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -56,6 +56,8 @@ struct RISCVVirtState
aa32 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -58,6 +58,7 @@ struct RISCVVirtState {
> int aia_guests;
> char *oem_id;
> char *oem_table_id;
> +OnOffAuto acpi;
> };
>
> enum {
> @@ -123,4 +124,5 @@ enum {
> #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
> 1 + FDT_APLIC_INT_CELLS)
>
> +bool virt_is_acpi_enabled(RISCVVirtState *s);
> #endif
> --
> 2.34.1
>
Otherwise,
Reviewed-by: Andrew Jones
Thanks,
drew
irt.h
> @@ -59,6 +59,7 @@ struct RISCVVirtState {
> char *oem_id;
> char *oem_table_id;
> OnOffAuto acpi;
> +const MemMapEntry *memmap;
> };
>
> enum {
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
On Mon, Feb 13, 2023 at 08:10:32PM +0530, Sunil V L wrote:
> Add few basic ACPI tables and DSDT with few devices in a
> new file virt-acpi-build.c.
>
> These are mostly leveraged from arm64.
>
> Signed-off-by: Sunil V L
> ---
> hw/riscv/virt-acpi-build.c | 285 ++
On Mon, Feb 13, 2023 at 08:10:33PM +0530, Sunil V L wrote:
> Add Multiple APIC Description Table (MADT) with the
> INTC structure for each cpu.
>
> Signed-off-by: Sunil V L
> Acked-by: Alistair Francis
> ---
> hw/riscv/virt-acpi-build.c | 37 +
> 1 file chang
*/
> +build_append_int_noprefix(table_data, 1, 2); /* number of
> offsets */
s/number/Number/
> +build_append_int_noprefix(table_data, acpi_proc_id, 4); /* UID */
ACPI Processor UID
> +build_append_int_noprefix(table_data, isa_offset, 4);
/* Offsets */
> +acpi_proc_id++;
> +}
> +}
> +
> +acpi_table_end(linker, &table);
> +}
> +
> /* FADT */
> static void
> build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
> --
> 2.34.1
>
Other than getting the comments to match the spec fields,
Reviewed-by: Andrew Jones
Thanks,
drew
;microchip_pfsoc.c'))
> +riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
>
> hw_arch += {'riscv': riscv_ss}
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
led()) {
> riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
> }
> +
> +if (virt_is_acpi_enabled(s)) {
> +virt_acpi_setup(s);
> +}
> }
>
> static void virt_machine_init(MachineState *machine)
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
gt; bool
> --
> 2.34.1
>
This could probably squashed together with the previous patch.
Reviewed-by: Andrew Jones
> +RISC-V ACPI Subsystem
> +M: Sunil V L
> +L: qemu-ri...@nongnu.org
> +S: Maintained
> +F: hw/riscv/virt-acpi-build.c
> +
> STM32F100
> M: Alexandre Iooss
> L: qemu-...@nongnu.org
> --
> 2.34.1
>
Please move the ARM ACPI entry down under the main ACPI entry and then
add the RISC-V one there too.
Otherwise,
Reviewed-by: Andrew Jones
target/riscv/cpu_helper.c | 6 +++---
> target/riscv/csr.c| 15 ++-
> target/riscv/machine.c| 11 ---
> target/riscv/monitor.c| 2 +-
> target/riscv/op_helper.c | 2 +-
> target/riscv/pmp.c| 8 ++++
> 9 files changed, 34 insertions(+), 66 deletions(-)
>
> --
> 2.39.1
>
>
For the series
Reviewed-by: Andrew Jones
On Wed, Feb 15, 2023 at 03:57:18PM -0300, Daniel Henrique Barboza wrote:
> At this moment, and apparently since ever, we have no way of enabling
> RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
> the nuts and bolts that handles how to properly write this CSR, has
> always b
On Thu, Feb 16, 2023 at 05:33:55PM +0800, Bin Meng wrote:
> On Thu, Feb 16, 2023 at 5:29 PM Andrew Jones wrote:
> >
> > On Wed, Feb 15, 2023 at 03:57:18PM -0300, Daniel Henrique Barboza wrote:
> > > At this moment, and apparently since ever, we have no way of enabling
-
> target/riscv/csr.c | 55 --
> 1 file changed, 55 deletions(-)
>
Reviewed-by: Andrew Jones
Thanks,
drew
FEATURE_DEBUG
> };
>
> --
> 2.39.1
>
Probably could squash into the previous patch, but anyway
Reviewed-by: Andrew Jones
Thanks,
drew
build_state, tables.table_data,
> + ACPI_BUILD_TABLE_FILE);
> +assert(build_state->table_mr != NULL);
> +
> +build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update,
> + build_state,
> + tables.linker->cmd_blob,
> + ACPI_BUILD_LOADER_FILE);
> +
> +build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
> + build_state, tables.rsdp,
> + ACPI_BUILD_RSDP_FILE);
> +
> +qemu_register_reset(virt_acpi_build_reset, build_state);
> +virt_acpi_build_reset(build_state);
> +vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
> +
> +/*
> + * Clean up tables but don't free the memory: we track it
> + * in build_state.
> + */
> +acpi_build_tables_cleanup(&tables, false);
> +}
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index 379501edcc..e5c474b26e 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -126,4 +126,5 @@ enum {
> 1 + FDT_APLIC_INT_CELLS)
>
> bool virt_is_acpi_enabled(RISCVVirtState *s);
> +void virt_acpi_setup(RISCVVirtState *vms);
> #endif
> --
> 2.34.1
>
Otherwise,
Reviewed-by: Andrew Jones
Thanks,
drew
; build_fadt_rev6(tables_blob, tables->linker, s, dsdt);
>
> +acpi_add_table(table_offsets, tables_blob);
> +build_madt(tables_blob, tables->linker, s);
> +
> /* XSDT is pointed to by RSDP */
> xsdt = tables_blob->len;
> build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
Thanks,
drew
t;
> Thanks,
>
>
> Daniel
>
> >
> >
> > Zhiwei
> >
> > > Given that allowing the dormant code to write MISA can cause tricky bugs
> > > to solve later on, and we don't have a particularly interesting case of
> > > wri
On Tue, Feb 21, 2023 at 03:22:45PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 2/21/23 14:06, Andrew Jones wrote:
> > On Tue, Feb 21, 2023 at 12:49:11PM -0300, Daniel Henrique Barboza wrote:
> > > Hey,
> > >
> > > On 2/16/23 22:42, LIU Zhiwei wrote:
mu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
> qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
> - 2, flashbase, 2, flashsize,
> - 2, flashbase + flashsize, 2, flashsize);
> + 2, flashbase[0], 2, flashsize[0],
> + 2, flashbase[1], 2, flashsize[1]);
> qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
> g_free(name);
> }
> --
> 2.38.0
>
>
Reviewed-by: Andrew Jones
On Mon, Nov 07, 2022 at 11:16:00AM +0530, Sunil V L wrote:
> On Sun, Nov 06, 2022 at 10:20:57PM +0300, Mike Maslenkin wrote:
> > Hello Sunil!
> >
> > What about virt_machine_done() function?
> > kernel_entry variable still points to the second flash started from
> > virt_memmap[VIRT_FLASH].size /
On Mon, Nov 07, 2022 at 04:19:10PM +, Daniel P. Berrangé wrote:
> On Mon, Nov 07, 2022 at 03:50:44PM +, Alex Bennée wrote:
> >
> > Sunil V L writes:
> >
> > > On Mon, Nov 07, 2022 at 01:06:38PM +, Peter Maydell wrote:
> > >> On Mon, 7 Nov 2022 at 13:03, Sunil V L wrote:
> > >> >
> >
On Tue, Nov 08, 2022 at 03:12:42PM +0100, Philippe Mathieu-Daudé wrote:
> On 7/11/22 18:34, Daniel P. Berrangé wrote:
> > On Mon, Nov 07, 2022 at 06:32:01PM +0100, Andrew Jones wrote:
> > > On Mon, Nov 07, 2022 at 04:19:10PM +, Daniel P. Berrangé wrote:
> > > >
On Fri, Oct 21, 2022 at 06:58:03AM +0100, Ben Dooks wrote:
> Add a helper to set a property from a set of strings
> to reduce the following code:
>
> static const char * const clint_compat[2] = {
> "sifive,clint0", "riscv,clint0"
> };
>
> qemu_fdt_setprop_string_array(fdt, nod
On Fri, Oct 21, 2022 at 06:58:02AM +0100, Ben Dooks wrote:
> Add a qemu_fdt_setprop_strings to set a string array into a device-tree.
>
> Only minor updates from v4 to fix a couple of minor patch issues.
Please see the comments I made on patch 1 of the v4 series, they should
be addressed. Also, I
osed to the guest.
>
> Mayuresh Chitale (3):
> update-linux-headers: Version 6.1-rc2
> target/riscv: Extend isa_ext_data for single letter extensions
> target/riscv: kvm: Support selecting VCPU extensions
>
I already reviewed this internally and it hasn't changed, so
for the se
On Mon, Feb 06, 2023 at 12:18:06PM +0100, Philippe Mathieu-Daudé wrote:
> On 6/2/23 11:54, Andrea Bolognani wrote:
> > On Thu, Feb 02, 2023 at 10:22:15AM +0530, Sunil V L wrote:
> > > +object_class_property_add(oc, "acpi", "OnOffAuto",
> > > + virt_get_acpi, virt_se
On Tue, Feb 07, 2023 at 11:57:29AM +0800, Bin Meng wrote:
> On Mon, Feb 6, 2023 at 8:36 PM Andrew Jones wrote:
> >
> > On Mon, Feb 06, 2023 at 12:18:06PM +0100, Philippe Mathieu-Daudé wrote:
> > > On 6/2/23 11:54, Andrea Bolognani wrote:
> > > > On Thu, Feb 02,
On Tue, Feb 07, 2023 at 09:50:29AM +0100, Philippe Mathieu-Daudé wrote:
> On 6/2/23 13:56, Gerd Hoffmann wrote:
> > On Mon, Feb 06, 2023 at 12:18:06PM +0100, Philippe Mathieu-Daudé wrote:
> > > On 6/2/23 11:54, Andrea Bolognani wrote:
> > > > On Thu, Feb 02, 2023 at 10:22:15AM +0530, Sunil V L wrot
On Mon, Feb 06, 2023 at 12:18:06PM +0100, Philippe Mathieu-Daudé wrote:
> On 6/2/23 11:54, Andrea Bolognani wrote:
> > On Thu, Feb 02, 2023 at 10:22:15AM +0530, Sunil V L wrote:
> > > +object_class_property_add(oc, "acpi", "OnOffAuto",
> > > + virt_get_acpi, virt_se
On Tue, Feb 07, 2023 at 06:38:15AM -0800, Andrea Bolognani wrote:
> On Tue, Feb 07, 2023 at 03:02:19PM +0100, Thomas Huth wrote:
> > On 07/02/2023 14.56, Andrea Bolognani wrote:
> > > It looks like i440fx and q35 both have an 'acpi' machine property. Is
> > > -no-acpi just sugar for acpi=off?
> >
>
CVState *env, int
> csrno,
> static RISCVException write_misa(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> -if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
> +if (!riscv_cpu_cfg(env)->misa_w) {
> /* drop write to misa */
> return RISCV_EXCP_NONE;
> }
> --
> 2.39.2
>
>
Reviewed-by: Andrew Jones
On Thu, Feb 23, 2023 at 04:13:57PM +0800, Gavin Shan wrote:
> For arm64 and RiscV architecture, the driver (/base/arch_topology.c) is
> used to populate the CPU topology in the Linux guest. It's required that
> the CPUs in one socket can't span mutiple NUMA nodes. Otherwise, the Linux
> scheduling
n Meng
> Acked-by: Alistair Francis
> Reviewed-by: Andrew Jones
> ---
> MAINTAINERS | 18 --
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9adb628627..7a47c2c724 100644
> --- a/MAINTAINERS
On Fri, Feb 24, 2023 at 09:16:39PM +1100, Gavin Shan wrote:
> On 2/24/23 8:26 PM, Daniel Henrique Barboza wrote:
> > On 2/24/23 04:09, Gavin Shan wrote:
> > > On 2/24/23 12:18 AM, Daniel Henrique Barboza wrote:
> > > > On 2/23/23 05:13, Gavin Shan wrote:
> > > > > For arm64 and RiscV architecture,
On Fri, Feb 24, 2023 at 12:08:48PM +0800, Weiwei Li wrote:
> henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/csr.c | 13 +
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> di
On Fri, Jan 06, 2023 at 08:56:33AM +0100, Alexandre Ghiti wrote:
> On Fri, Dec 16, 2022 at 2:03 PM Alexandre Ghiti
> wrote:
...
> @Andrew: Please let me know when you have some cycles to review this,
I'll try to get to this yet today. Thanks for the ping.
drew
On Mon, Dec 12, 2022 at 11:22:50AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
mething unexpected happened,
> so we should return an error.
>
> Added SBI related return code's defines.
>
> Signed-off-by: Alexei Filippov
> Fixes: 4eb47125 ("target/riscv: Handle KVM_EXIT_RISCV_SBI exit")
> ---
> Changes since v7:
> - Fix
On Tue, Aug 06, 2024 at 11:51:20AM GMT, Alistair Francis wrote:
> On Wed, Jul 24, 2024 at 9:33 AM Atish Patra wrote:
> >
> > Sscofpmf has been supported on virt machine for a long time. It is
> > required to enable profiling on virt machines. Let's enable it
> > by default for ease of usage.
> >
>
On Tue, Jul 23, 2024 at 04:30:10PM GMT, Atish Patra wrote:
> Counter delegation/configuration extension requires the following
> extensions to be enabled.
>
> 1. Smcdeleg - To enable counter delegation from M to S
> 2. S[m|s]csrind - To enable indirect access CSRs
> 3. Smstateen - Indirect CSR ext
resses may be up to 34 bits wide, so we don't want to
clear the high bits while page aligning the address. The fix is to
revert to using target_long, since a signed type will get extended.
Fixes: af3fc195e3c8 ("target/riscv: Change the TLB page size depends on PMP
entries.")
Si
On Tue, Aug 13, 2024 at 05:43:07PM GMT, Richard Henderson wrote:
> On 8/13/24 17:13, Andrew Jones wrote:
> > C doesn't extend the sign bit for unsigned types since there isn't a
> > sign bit to extend. This means a promotion of a u32 to a u64 results
> > in the uppe
On Tue, Aug 13, 2024 at 10:21:13AM GMT, Philippe Mathieu-Daudé wrote:
> On 13/8/24 10:00, Andrew Jones wrote:
> > On Tue, Aug 13, 2024 at 05:43:07PM GMT, Richard Henderson wrote:
> > > On 8/13/24 17:13, Andrew Jones wrote:
> > > > C doesn't extend the sign bit f
t DT and know their software supports it, introduce a machine
property 'strict-dt' to do so. We also drop the one redundant
property that uses a deprecated name when strict-dt is enabled.
Signed-off-by: Andrew Jones
---
docs/system/riscv/virt.rst | 11 ++
hw/riscv/virt.c
16124957.130017-2-ajo...@ventanamicro.com/ # 1
Signed-off-by: Andrew Jones
---
hw/riscv/virt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 9981e0f6c9b9..cef41c150aaf 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -552,7 +552,6 @@ static void create_fdt_one_im
9.1 since
it's a fix. The second patch allows users to bring it back by enabling
a new machine property 'strict-dt' which is meant to be used for cases
like these going forward. There's no rush for the second patch.
[1] https://lore.kernel.org/all/20240816124957.130017-2-ajo..
On Thu, Aug 01, 2024 at 12:43:24PM GMT, Daniel Henrique Barboza wrote:
> From: Tomasz Jeznach
>
> The RISC-V IOMMU specification is now ratified as-per the RISC-V
> international process. The latest frozen specifcation can be found at:
>
> https://github.com/riscv-non-isa/riscv-iommu/releases/do
On Mon, Aug 19, 2024 at 11:19:18AM GMT, Alistair Francis wrote:
> On Sat, Aug 17, 2024 at 2:08 AM Andrew Jones wrote:
> >
> > Older firmwares and OS kernels which use deprecated device tree
> > properties or are missing support for new properties may not be
> > toleran
bit setting.
Signed-off-by: Andrew Jones
---
target/riscv/kvm/kvm-cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index f6e3156b8d2f..341af901c5b0 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm
Add appropriate commit message.
> - Fix error handling according to Andrew Jones suggestion.
> target/riscv/kvm/kvm-cpu.c | 11 +++
> target/riscv/sbi_ecall_interface.h | 12
> 2 files changed, 19 insertions(+), 4 deletions(-)
>
>
On Mon, May 27, 2024 at 02:19:13AM GMT, Chao Du wrote:
> This patch implements insert/remove software breakpoint process:
>
> Add an input parameter for kvm_arch_insert_sw_breakpoint() and
> kvm_arch_remove_sw_breakpoint() to pass the length information,
> which helps us to know whether it is a RV
On Mon, May 27, 2024 at 02:19:14AM GMT, Chao Du wrote:
> Set the control flag when there are active breakpoints. This will
> help KVM to know the status in the userspace.
>
> Signed-off-by: Chao Du
> ---
> target/riscv/kvm/kvm-cpu.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
>
case KVM_EXIT_RISCV_CSR:
> ret = kvm_riscv_handle_csr(cs, run);
> break;
> +case KVM_EXIT_DEBUG:
> +if (kvm_riscv_handle_debug(cs)) {
> +ret = EXCP_DEBUG;
> +}
> +break;
> default:
> qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
>__func__, run->exit_reason);
> --
> 2.17.1
>
>
Reviewed-by: Andrew Jones
GET_KVM_HAVE_GUEST_DEBUG=y
> TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml
> gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
> TARGET_NEED_FDT=y
> --
> 2.17.1
>
>
Reviewed-by: Andrew Jones
ve_hw_breakpoint(vaddr addr, vaddr len, int type)
> +{
> +/* TODO; To be implemented later. */
> +return -EINVAL;
> +}
> +
> +void kvm_arch_remove_all_hw_breakpoints(void)
> +{
> +/* TODO; To be implemented later. */
> +}
> +
> +void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
> +{
> +if (kvm_sw_breakpoints_active(cs)) {
> +dbg->control |= KVM_GUESTDBG_ENABLE;
> +}
> +}
> --
> 2.17.1
>
Reviewed-by: Andrew Jones
On Thu, May 30, 2024 at 11:30:28AM GMT, Fea Wang wrote:
> Hi Daniel,
> thank you for your help.
>
> I found that only the cover is without many maintainers. I used to send
> patches by git send-email --dry-run --to 'qemu-devel@nongnu.org,
> qemu-ri...@nongnu.org' --cc-cmd='scripts/get_maintainer.p
On Thu, May 30, 2024 at 05:49:49AM GMT, Daniel Henrique Barboza wrote:
> We need #address-cells properties in all interrupt controllers that are
> referred by an interrupt-map [1]. For the RISC-V machine, both PLIC and
> APLIC controllers must have this property.
>
> PLIC already sets it in create
On Thu, May 30, 2024 at 01:05:41PM GMT, Andrew Jones wrote:
> On Thu, May 30, 2024 at 05:49:49AM GMT, Daniel Henrique Barboza wrote:
> > We need #address-cells properties in all interrupt controllers that are
> > referred by an interrupt-map [1]. For the RISC-V machine, both PLI
On Wed, Jan 17, 2024 at 07:54:12PM +0530, Himanshu Chauhan wrote:
> This patch adds "x-sdtrig" in the ISA string when sdtrig extension is enabled.
> The sdtrig extension may or may not be implemented in a system. Therefore, the
> -cpu rv64,x-sdtrig=
> option can be used to dynamically t
On Mon, Jan 22, 2024 at 03:42:10PM +1000, Alistair Francis wrote:
> > > From memory the "debug" property is for the original debug spec:
> > > https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote
> > >
> > > That was ratified and is an official extension. AFAIK this is what is
> >
gt; +}
> +}
> +
> static void virt_machine_done(Notifier *notifier, void *data)
> {
> RISCVVirtState *s = container_of(notifier, RISCVVirtState,
> @@ -1337,6 +1377,8 @@ static void virt_machine_done(Notifier *notifier, void
> *data)
> riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
> }
>
> +virt_build_smbios(s);
> +
> if (virt_is_acpi_enabled(s)) {
> virt_acpi_setup(s);
> }
> --
> 2.43.0
>
>
Otherwise,
Reviewed-by: Andrew Jones
Thanks,
drew
"-smbios
> type=8[,external_reference=str][,internal_reference=str][,connector_type=%d][,port_type=%d]\n"
> "specify SMBIOS type 8 fields\n"
> @@ -2722,7 +2722,7 @@ SRST
> ``-smbios
> type=3[,manufacturer=str][,version=str][,serial=str][,asset=str][,sku=str]``
> Specify SMBIOS type 3 fields
>
> -``-smbios
> type=4[,sock_pfx=str][,manufacturer=str][,version=str][,serial=str][,asset=str][,part=str][,processor-id=%d]``
> +``-smbios
> type=4[,sock_pfx=str][,manufacturer=str][,version=str][,serial=str][,asset=str][,part=str][,processor-family=%d][,processor-id=%d]``
> Specify SMBIOS type 4 fields
>
> ``-smbios type=11[,value=str][,path=filename]``
> --
> 2.43.0
>
>
Reviewed-by: Andrew Jones
e_legacy(MachineState *ms, size_t *length);
> void smbios_get_tables(MachineState *ms,
> const struct smbios_phys_mem_area *mem_array,
> --
> 2.43.0
>
>
Reviewed-by: Andrew Jones
QEMU_ARCH_I386 | QEMU_ARCH_ARM | QEMU_ARCH_LOONGARCH | QEMU_ARCH_RISCV)
> SRST
> ``-smbios file=binary``
> Load SMBIOS entry from binary file.
> --
> 2.43.0
>
>
Reviewed-by: Andrew Jones
On Mon, Jan 22, 2024 at 01:28:18PM +0100, Heinrich Schuchardt wrote:
> On 22.01.24 10:57, Andrew Jones wrote:
> > On Fri, Dec 29, 2023 at 01:07:23PM +0100, Heinrich Schuchardt wrote:
...
> > > +#if defined(TARGET_RISCV32)
> > > +smbios_set_default_processor_family(0
On Mon, Jan 22, 2024 at 02:55:50PM +, Alex Bennée wrote:
> From: Akihiko Odaki
>
> The effective MXL value matters when booting.
I'd prefer this commit message get some elaboration. riscv_is_32bit()
is used in a variety of contexts, some where it should be reporting
the max misa.mxl. However
On Mon, Jan 22, 2024 at 02:07:57PM +0100, Heinrich Schuchardt wrote:
> Generate SMBIOS tables for the RISC-V mach-virt.
> Add CONFIG_SMBIOS=y to the RISC-V default config.
> Set the default processor family in the type 4 table.
>
> The implementation is based on the corresponding ARM and Loongson
misa_mxl_max to determine bitness
> v2:
> set processor family
> ---
> hw/riscv/Kconfig | 1 +
> hw/riscv/virt.c | 42 ++++++
> 2 files changed, 43 insertions(+)
>
Reviewed-by: Andrew Jones
On Wed, Jan 24, 2024 at 12:08:33PM +0900, Akihiko Odaki wrote:
> On 2024/01/23 17:20, Andrew Jones wrote:
> > On Mon, Jan 22, 2024 at 02:55:50PM +, Alex Bennée wrote:
> > > From: Akihiko Odaki
> > >
> > > The effective MXL value matters when booting.
>
riscv/gdbstub.c
> index 58b3ace0fe..f15980fdcf 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -218,7 +218,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int
> base_reg)
> CPURISCVState *env = &cpu->env;
> GString *s = g_string_new(NULL);
> riscv_csr_predicate_fn predicate;
> -int bitsize = 16 << env->misa_mxl_max;
> +int bitsize = riscv_cpu_max_xlen(*env);
> int i;
>
> #if !defined(CONFIG_USER_ONLY)
> --
> 2.43.0
>
Otherwise,
Reviewed-by: Andrew Jones
On Thu, Jan 25, 2024 at 05:23:20PM +0900, Akihiko Odaki wrote:
> On 2024/01/24 17:16, Andrew Jones wrote:
> > On Wed, Jan 24, 2024 at 12:08:33PM +0900, Akihiko Odaki wrote:
> > > On 2024/01/23 17:20, Andrew Jones wrote:
> > > > On Mon, Jan 22, 2024 at 02:55
On Thu, Jan 25, 2024 at 04:53:19PM -0300, Daniel Henrique Barboza wrote:
> From: Andrew Jones
>
> Named features are extensions which don't make sense for users to
> control and are therefore not exposed on the command line. However,
> svade is an extension which makes sense
Add *envcfg.HADE related check in address
translation")
Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension")
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Andrew Jones
---
target/riscv/cpu.c | 3 +--
target/riscv/csr.c | 2 +-
2 files changed, 2 ins
From: Daniel Henrique Barboza
Recent changes in options handling removed the 'mmu' default the bare
CPUs had, meaning that we must enable 'mmu' by hand when using the
rva22s64 profile CPU.
Given that this profile is setting a satp mode, it already implies that
we need a 'mmu'. Enable the 'mmu' i
pdating
(this behavior change fixes [2])
Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address
translation") [1]
Fixes: 48531f5adb2a ("target/riscv: implement svade") [2]
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Andrew Jones
---
targe
cv/riscv-profiles/issues/121
[2] https://github.com/riscv/riscv-profiles/issues/142
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 17 +
target/riscv/cpu_cfg.h | 6 --
target/riscv/tcg/tcg-cpu.c | 16 ++---
tree/cpus/cpu@0/riscv,isa
rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_
zicntr_zicsr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zca_zcd_zba_zbb_
zbs_zkt_sscounterenw_sstvala_sstvecd_svade_svinval_svpbmt#
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
e' is promoted to a regular extension and all
the named features QEMU implements are now being displayed in riscv,isa.
v2:
- Ensure svade is off by default even for the max cpu type
Andrew Jones (3):
target/riscv: Reset henvcfg to zero
target/riscv: Gate hardware A/D PTE bit updating
target
since QEMU has always implemented hardware A/D PTE bit
updating, so users must opt into svade (or get it from a CPU type
which enables it by default).
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Andrew Jones
---
target/riscv/cpu.c | 8 +++-
target/riscv/tcg/tcg-cpu.c | 6
On Wed, May 15, 2024 at 02:25:31PM GMT, Eric Cheng wrote:
> On 3/8/2024 12:03 AM, Daniel Henrique Barboza wrote:
> > From: Tomasz Jeznach
> >
> > Generate device tree entry for riscv-iommu PCI device, along with
> > mapping all PCI device identifiers to the single IOMMU device instance.
> >
> >
;max_hart_per_socket, BITS_PER_LONG) + 1;
> +} else {
> +hart_bits = 0;
> +}
> +
> ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
> KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
> &hart_bits, true, NULL);
> --
> 2.17.1
>
Reviewed-by: Andrew Jones
On Tue, Mar 12, 2024 at 09:52:20PM GMT, Wu, Fei2 wrote:
> The harts requirements of RISC-V server platform [1] require RVA23 ISA
> profile support, plus Sv48, Svadu, H, Sscofmpf etc. This patch provides
> a virt CPU type (rvsp-ref) as compliant as possible.
We should add the RVA23 profile cpu type
On Tue, Mar 12, 2024 at 09:52:21PM GMT, Fei Wu wrote:
> The RISC-V Server Platform specification[1] defines a standardized set
> of hardware and software capabilities, that portable system software,
> such as OS and hypervisors can rely on being present in a RISC-V server
> platform.
>
> A corresp
- removed 'gpa' boolean from riscv_iommu_spa_fetch()
>> - 'en_s' is no longer used for early MSI address match
>>
>> - patch 10:
>> - add ATS steps in riscv_iommu_validate_device_ctx()
>> - check for 's->enable_ats' before adding RISCV
deliver
an interrupt at that previous timecmp time. Ensure the stopped timer
will not still deliver an interrupt by also deleting the QEMU timer
in the UINT64_MAX special case.
Fixes: ae0edf2188b3 ("target/riscv: No need to re-start QEMU timer when timecmp
== UINT64_MAX")
Signed-off-by: Andre
On Fri, Aug 30, 2024 at 02:05:05PM GMT, Vladimir Isaev wrote:
> Hi Andrew,
>
> 29.08.2024 11:40, Andrew Jones wrote:
> > While the spec doesn't state it, setting timecmp to UINT64_MAX is
> > another way to stop a timer, as it's considered setting the next
>
resses may be up to 34 bits wide, so we don't want to
clear the high bits while page aligning the address. The fix is to
use hwaddr for the mask, which, even on rv32, is 64-bits wide.
Fixes: af3fc195e3c8 ("target/riscv: Change the TLB page size depends on PMP
entries.")
Signed-off-
On Mon, Sep 09, 2024 at 12:41:24PM GMT, Alistair Francis wrote:
> On Mon, Aug 19, 2024 at 5:50 PM Andrew Jones wrote:
> >
> > On Mon, Aug 19, 2024 at 11:19:18AM GMT, Alistair Francis wrote:
> > > On Sat, Aug 17, 2024 at 2:08 AM Andrew Jones
> > > wrote:
>
On Mon, Sep 16, 2024 at 08:16:33PM GMT, Heinrich Schuchardt wrote:
> OpenSBI enables the floating point in mstatus. For consistency QEMU/KVM
> should do the same.
>
> Without this patch EDK II with TLS enabled crashes when hitting the first
> floating point instruction while running QEMU with --ac
On Tue, Sep 17, 2024 at 02:54:33PM GMT, Alexei Filippov wrote:
> kvm_riscv_handle_sbi() may return not supported return code to not
> trigger qemu abort with vendor-specific sbi.
>
> Add new error path to provide proper error in case of
> qemu_chr_fe_read_all() may not return sizeof(ch), because e
On Mon, Sep 09, 2024 at 01:27:05PM GMT, Alistair Francis wrote:
> On Tue, Aug 6, 2024 at 7:05 AM Gregor Haas wrote:
> >
> > This patch series adds support for specifying OpenSBI domains on the QEMU
> > command line. A simple example of what this looks like is below, including
> > mapping the board
On Tue, Sep 17, 2024 at 02:29:41PM GMT, Andrew Jones wrote:
> On Tue, Sep 17, 2024 at 02:54:33PM GMT, Alexei Filippov wrote:
> > kvm_riscv_handle_sbi() may return not supported return code to not
> > trigger qemu abort with vendor-specific sbi.
> >
> > Add new error p
On Tue, Sep 17, 2024 at 03:28:42PM GMT, Heinrich Schuchardt wrote:
> On 17.09.24 14:13, Andrew Jones wrote:
> > On Mon, Sep 16, 2024 at 08:16:33PM GMT, Heinrich Schuchardt wrote:
> > > OpenSBI enables the floating point in mstatus. For consistency QEMU/KVM
> &
/meson.build | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
Reviewed-by: Andrew Jones
} else {
> +vms->gic_version = VIRT_GIC_VERSION_2;
> +}
> break;
> case VIRT_GIC_VERSION_HOST:
> error_report("gic-version=host requires KVM");
> --
> 2.26.3
>
Reviewed-by: Andrew Jones
te *env, int csrno)
> {
> if (riscv_cpu_mxl(env) != MXL_RV32) {
> -if (!riscv_cpu_virt_enabled(env)) {
> -return RISCV_EXCP_ILLEGAL_INST;
> - } else {
> -return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> -}
> +return RISCV_EXCP_ILLEGAL_INST;
> }
>
> return hmode(env, csrno);
> --
> 2.17.1
>
>
Otherwise,
Reviewed-by: Andrew Jones
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