On 9/18/20 4:38 PM, Eduardo Habkost wrote:
> On Mon, Aug 31, 2020 at 01:43:07PM -0500, Babu Moger wrote:
>> apic_id contains all the information required to build
>> CPUID_8000_001E. core_id and node_id is already part of
>> apic_id generated by x86_topo_ids_from_apic
.org
> Subject: Re: [PATCH v7 07/13] hw/386: Add EPYC mode topology decoding
> functions
>
> Hi,
>
> It looks like this series breaks -device and CPU hotplug:
>
> On Wed, Mar 11, 2020 at 05:53:34PM -0500, Babu Moger wrote:
> > These functions add support for building E
: Initialize topo_ids from
> CpuInstanceProperties
>
> On Mon, 27 Jul 2020 18:59:42 -0500
> Babu Moger wrote:
>
> > > -Original Message-
> > > From: Igor Mammedov
> > > Sent: Monday, July 27, 2020 12:14 PM
> > > To: Moger, Babu
> > &g
Remove node_id, nr_nodes and nodes_per_pkg from topology. Use
die_id, nr_dies and dies_per_pkg which is already available.
Removes the confusion over two variables.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 -
hw/i386/x86.c |1 -
include/hw/i386/topology.h
Adding a new check to warn the users to configure 'dies' when
topology is numa configured. It makes it easy to build the
topology for EPYC models.
Signed-off-by: Babu Moger
---
hw/i386/x86.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index
Link below.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 77 +
1 file changed, 36 insertions(+), 41 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 588f32e136..c892432cae 100644
--- a/target/i386/cpu.c
+++ b/target
the apic_id suggested by Igor.
- Also did some minor code re-aarangement to take care of changes.
- Dropped the patch "Simplify CPUID_8000_001E" from v1. Will send
it later.
v1:
https://lore.kernel.org/qemu-devel/159164739269.20543.3074052993891532749.st...@naples-babu.amd.com
Bab
On 8/7/20 11:52 AM, Daniel P. Berrangé wrote:
> On Fri, Aug 07, 2020 at 11:32:51AM -0500, Babu Moger wrote:
>> Adding a new check to warn the users to configure 'dies' when
>> topology is numa configured. It makes it easy to build the
>> topology for EPYC models.
>
&
On 8/7/20 2:11 PM, Igor Mammedov wrote:
> On Fri, 7 Aug 2020 17:52:22 +0100
> Daniel P. Berrangé wrote:
>
>> On Fri, Aug 07, 2020 at 11:32:51AM -0500, Babu Moger wrote:
>>> Adding a new check to warn the users to configure 'dies' when
>>> topology is numa conf
to configure smp dies for
> EPYC
>
> On Fri, 07 Aug 2020 11:32:51 -0500
> Babu Moger wrote:
>
> > Adding a new check to warn the users to configure 'dies' when
> s/warn .../error out .../
>
> > topology is numa configured. It makes it easy to build the topolog
2/3] hw/i386: Add a new check to configure smp dies for
> EPYC
>
> On Tue, 11 Aug 2020 16:03:58 -0500
> Babu Moger wrote:
>
> > On 8/7/20 2:11 PM, Igor Mammedov wrote:
> > > On Fri, 7 Aug 2020 17:52:22 +0100
> > > Daniel P. Berrangé wrote:
> >
d memory with -device and CPU
> hotplug
>
>
>
> On 6/25/20 1:32 PM, Igor Mammedov wrote:
> > On Thu, 25 Jun 2020 11:41:25 -0500
> > Babu Moger wrote:
> >
> >> Igor,
> >>
> >>> -Original Message-
> >>> From: Ig
This is in preparation to build the apic_id from user
provided topology information.
Signed-off-by: Babu Moger
---
include/hw/i386/topology.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 07239f95f4
-by: Babu Moger
---
hw/i386/pc.c |6 +-
hw/i386/x86.c | 19 +--
include/hw/i386/topology.h | 14 +++---
include/hw/i386/x86.h |6 --
tests/test-x86-cpuid.c | 39 ---
5 files
=1828750
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index e613b2299f..aa9fb48834 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1553,6 +1553,15 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev
rties
>
> On Wed, 01 Jul 2020 12:31:08 -0500
> Babu Moger wrote:
>
> > Build apic_id from CpuInstanceProperties if numa configured.
> > Use the node_id from user provided numa information. This will avoid
> > conflicts between numa information and apic_id generat
t; CpuInstanceProperties
>
> On Wed, 01 Jul 2020 12:31:01 -0500
> Babu Moger wrote:
>
> > This is in preparation to build the apic_id from user provided
> > topology information.
> >
> > Signed-off-by: Babu Moger
> > ---
> > include/hw/i386/
t; CpuInstanceProperties
>
> On Mon, 13 Jul 2020 11:43:33 -0500
> Babu Moger wrote:
>
> > On 7/13/20 11:17 AM, Igor Mammedov wrote:
> > > On Mon, 13 Jul 2020 10:02:22 -0500
> > > Babu Moger wrote:
> > >
> > >>> -Original M
On 7/13/20 11:17 AM, Igor Mammedov wrote:
> On Mon, 13 Jul 2020 10:02:22 -0500
> Babu Moger wrote:
>
>>> -Original Message-
>>> From: Igor Mammedov
>>> Sent: Monday, July 13, 2020 4:08 AM
>>> To: Moger, Babu
>>> Cc: pbonz...@r
t; CpuInstanceProperties
>
> On Mon, 13 Jul 2020 14:30:29 -0500
> Babu Moger wrote:
>
> > > -Original Message-
> > > From: Igor Mammedov
> > > Sent: Monday, July 13, 2020 12:32 PM
> > > To: Moger, Babu
> > > Cc: pbonz...@redhat.com; r...
the apic_id suggested by Igor.
- Also did some minor code re-aarangement to take care of changes.
- Dropped the patch "Simplify CPUID_8000_001E" from v1. Will send
it later.
v1:
https://lore.kernel.org/qemu-devel/159164739269.20543.3074052993891532749.st...@naples-babu.amd.co
> -Original Message-
> From: no-re...@patchew.org
> Sent: Friday, June 19, 2020 9:46 AM
> To: Moger, Babu
> Cc: pbonz...@redhat.com; r...@twiddle.net; ehabk...@redhat.com; qemu-
> de...@nongnu.org
> Subject: Re: [PATCH] target/i386: Remove core_id assert check in CPUID
> 0x801E
>
ort more than 255 cores we need x2apic support.
In that case topology is coming from CPUID 0xB which appears to
work fine.
Remove the assert check and fix the problem.
Fixes the bug:
Link: https://bugzilla.redhat.com/show_bug.cgi?id=1834200
Signed-off-by: Babu Moger
---
target/i386/cpu.c |
d memory with -device and CPU
> hotplug
>
> On Wed, 24 Jun 2020 12:35:59 -0500
> Babu Moger wrote:
>
> > > -Original Message-
> > > From: Igor Mammedov
> > > Sent: Wednesday, June 24, 2020 8:48 AM
> > > To: Moger, Babu
> >
d memory with -device and CPU
> hotplug
>
> On Tue, 16 Jun 2020 12:18:56 -0500
> Babu Moger wrote:
>
> > > -Original Message-
> > > From: Igor Mammedov
> > > Sent: Tuesday, June 16, 2020 5:59 AM
> > > To: Moger, Babu
> > > Cc:
On 6/25/20 1:32 PM, Igor Mammedov wrote:
> On Thu, 25 Jun 2020 11:41:25 -0500
> Babu Moger wrote:
>
>> Igor,
>>
>>> -Original Message-
>>> From: Igor Mammedov
>>> Sent: Thursday, June 25, 2020 10:19 AM
>>> To: Moger, Babu
d memory with -device and CPU
> hotplug
>
>
>
> On 6/25/20 1:32 PM, Igor Mammedov wrote:
> > On Thu, 25 Jun 2020 11:41:25 -0500
> > Babu Moger wrote:
> >
> >> Igor,
> >>
> >>> -Original Message-
> >>> From: Ig
ATCH 1/2] hw/386: Fix uninitialized memory with -device and CPU
> hotplug
>
> On Mon, 08 Jun 2020 15:18:50 -0500
> Babu Moger wrote:
>
> > Noticed the following command failure while testing CPU hotplug.
> >
> > $ qemu-system-x86_64 -machine q35,accel=kvm -smp 1,maxcpus=2
..@tripleback.net; ge...@hostfission.com; Dr. David
> Alan Gilbert
> Subject: Re: [PATCH v13 1/5] i386: Add support for CPUID_8000_001E for AMD
>
> On Fri, Jun 08, 2018 at 06:56:17PM -0400, Babu Moger wrote:
> > Add support for cpuid leaf CPUID_8000_001E. Build the config that cl
..@tripleback.net; ge...@hostfission.com; Dr. David
> Alan Gilbert
> Subject: Re: [PATCH v13 1/5] i386: Add support for CPUID_8000_001E for AMD
>
> On Thu, Jun 04, 2020 at 09:06:27AM -0500, Babu Moger wrote:
> >
> >
> > > -Original Message-
> > >
.
Refer the Processor Programming Reference (PPR) documentation
available from the bugzilla Link below.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 78 +
1 file changed, 37
is uninitialized while calling
apicid_from_topo_ids. The problem is discussed in the thread below.
https://lore.kernel.org/qemu-devel/20200602171838.gg577...@habkost.net/
Fix the problem by initializing the node_id properly.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |2 ++
include/hw
-devel/20200602175212.gh577...@habkost.net/
https://lore.kernel.org/qemu-devel/20200602175212.gh577...@habkost.net/
---
Babu Moger (2):
hw/386: Fix uninitialized memory with -device and CPU hotplug
i386: Simplify CPUID_8000_001E for AMD
hw/i386/pc.c |2 +
include/hw/i386
/13] hw/386: Add EPYC mode topology decoding
> functions
>
> On Tue, Jun 02, 2020 at 04:59:19PM -0500, Babu Moger wrote:
> >
> >
> > > -Original Message-
> > > From: Eduardo Habkost
> > > Sent: Tuesday, June 2, 2020 12:19 PM
> > >
On 6/3/20 10:31 AM, Eduardo Habkost wrote:
> On Wed, Jun 03, 2020 at 10:22:10AM -0500, Babu Moger wrote:
>>
>>
>>> -Original Message-
>>> From: Eduardo Habkost
>>> Sent: Tuesday, June 2, 2020 6:01 PM
>>> To: Moger, Babu
>>
On 6/3/20 10:45 AM, Eduardo Habkost wrote:
> On Wed, Jun 03, 2020 at 10:38:46AM -0500, Babu Moger wrote:
>>
>>
>> On 6/3/20 10:31 AM, Eduardo Habkost wrote:
>>> On Wed, Jun 03, 2020 at 10:22:10AM -0500, Babu Moger wrote:
>>>>
>>>>
>&g
v7 07/13] hw/386: Add EPYC mode topology decoding
> functions
>
> On Wed, Jun 03, 2020 at 10:38:46AM -0500, Babu Moger wrote:
> >
> >
> > On 6/3/20 10:31 AM, Eduardo Habkost wrote:
> > > On Wed, Jun 03, 2020 at 10:22:10AM -0500, Babu Moger wrote:
> > >
/13] hw/386: Add EPYC mode topology decoding
> functions
>
> On Tue, Jun 02, 2020 at 04:59:19PM -0500, Babu Moger wrote:
> >
> >
> > > -Original Message-
> > > From: Eduardo Habkost
> > > Sent: Tuesday, June 2, 2020 12:19 PM
> > >
redhat.com;
> r...@twiddle.net; mtosa...@redhat.com; qemu-devel@nongnu.org;
> k...@vger.kernel.org; k...@tripleback.net; ge...@hostfission.com; Dr. David
> Alan Gilbert
> Subject: Re: [PATCH v13 1/5] i386: Add support for CPUID_8000_001E for AMD
>
> On Fri, Jun 08, 2018 at 0
/13] hw/386: Add EPYC mode topology decoding
> functions
>
> Hi,
>
> It looks like this series breaks -device and CPU hotplug:
>
> On Wed, Mar 11, 2020 at 05:53:34PM -0500, Babu Moger wrote:
> > These functions add support for building EPYC mode topology given the
t; CpuInstanceProperties
>
> On Mon, 13 Jul 2020 14:30:29 -0500
> Babu Moger wrote:
>
> > > -Original Message-
> > > From: Igor Mammedov
> > > Sent: Monday, July 13, 2020 12:32 PM
> > > To: Moger, Babu
> > > Cc: pbonz...@redhat.com; r...
t; CpuInstanceProperties
>
> On Mon, 27 Jul 2020 10:49:08 -0500
> Babu Moger wrote:
>
> > > -Original Message-
> > > From: Igor Mammedov
> > > Sent: Friday, July 24, 2020 12:05 PM
> > > To: Moger, Babu
> > > Cc: qemu-devel@nongnu.org; pbo
Restricted Speculation
ssbd: Speculative Store Bypass Disable
erms: Enhanced REP MOVSB/STOSB support
fsrm: Fast Short REP MOVSB support
invpcid : Invalidate processor context ID
pku : Protection keys support
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 105
David, Are you still working on v2 of these series? I was going to test
and review. Thanks
> -Original Message-
> From: David Edmondson
> Sent: Tuesday, June 8, 2021 3:25 AM
> To: qemu-devel@nongnu.org
> Cc: k...@vger.kernel.org; Eduardo Habkost ; Paolo
> Bonzini ; Marcelo Tosatti ;
>
On 6/29/21 9:06 AM, Dr. David Alan Gilbert wrote:
> * zhenwei pi (pizhen...@bytedance.com) wrote:
>> A AMD server typically has cpuid level 0x10(test on Rome/Milan), it
>> should not be changed to 0x1f in multi-dies case.
>>
>> Fixes: a94e1428991 (target/i386: Add CPUID.1F generation support
>>
Hi Wei,
I dont know the background of this feature. I will let some else to
comment on that.
The patch exposes the feature TscInvariant to the guest successfully.
Tested it on my AMD box. I have few comments on your patch below.
On 4/23/21 12:32 AM, Wei Huang wrote:
> There was a customer
t/_is_intercept)")
a90c1ed9f11d ("(pcid) KVM: nSVM: Remove unused field")
fa44b82eb831 ("KVM: x86: Move MPK feature detection to common code")
38f3e775e9c2 ("x86/Kconfig: Update config and kernel doc for MPK feature on
AMD")
37486135d3a7 ("KVM: x86:
, Eduardo Habkost wrote:
> On Fri, Jan 22, 2021 at 10:36:27AM -0600, Babu Moger wrote:
>> Adds the support for AMD 3rd generation processors. The model
>> display for the new processor will be EPYC-Milan.
>>
>> Adds the following new feature bits on top of the feature bits f
> -Original Message-
> From: Pankaj Gupta
> Sent: Monday, March 1, 2021 2:22 PM
> To: Moger, Babu
> Cc: Pankaj Gupta ; Paolo Bonzini
> ; richard.hender...@linaro.org; Eduardo Habkost
> ; Qemu Developers
> Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation
>
Pankaj,
> -Original Message-
> From: Pankaj Gupta
> Sent: Monday, March 1, 2021 10:46 AM
> To: Pankaj Gupta
> Cc: Moger, Babu ; Paolo Bonzini
> ; richard.hender...@linaro.org; Eduardo Habkost
> ; Qemu Developers
> Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd
Hi Pankaj,
> -Original Message-
> From: Pankaj Gupta
> Sent: Wednesday, February 24, 2021 2:19 AM
> To: Moger, Babu
> Cc: Paolo Bonzini ; richard.hender...@linaro.org;
> Eduardo Habkost ; Qemu Developers de...@nongnu.org>
> Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd
issue at my end, Sorry! for the confusion.
> Can you please post the official patch for inclusion.
>
> Best regards,
> Pankaj
>
> On Mon, Mar 1, 2021 at 9:38 PM Babu Moger wrote:
>>
>>
>>
>>> -Original Message-
>>> From: Pankaj Gupt
by machine type)
x86 EPYC-Rome-v1 AMD EPYC-Rome Processor
x86 EPYC-Rome-v2 AMD EPYC-Rome Processor
Reported-by: Pankaj Gupta
Signed-off-by: Babu Moger
Signed-off-by: Pankaj Gupta
---
target/i386/cpu.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/target
On 3/3/21 3:42 AM, David Edmondson wrote:
> On Tuesday, 2021-03-02 at 15:20:00 -06, Babu Moger wrote:
>
>> Found the following cpu feature bits missing from EPYC-Rome model.
>> ibrs: Indirect Branch Restricted Speculation
>> ssbd: Speculative Store Bypass
by machine type)
x86 EPYC-Rome-v1 AMD EPYC-Rome Processor
x86 EPYC-Rome-v2 AMD EPYC-Rome Processor
Reported-by: Pankaj Gupta
Signed-off-by: Babu Moger
Signed-off-by: Pankaj Gupta
---
v2: Model-id remains same between EPYC-Rome-v1 and EPYC-Rome-v2.
Removed model-id in the patch
cept_dr to generic intercepts")
>> 03bfeeb988a9 ("KVM: SVM: Change intercept_cr to generic intercepts")
>> c45ad7229d13 ("KVM: SVM: Introduce
>> vmcb_(set_intercept/clr_intercept/_is_intercept)")
>> a90c1ed9f11d ("(pcid) KVM: nSVM: Remove u
I remember seeing something similar before. This was supposed to be
fixed by the linux kernel commit.
commit 841c2be09fe4f495fe5224952a419bd8c7e5b455
Author: Maxim Levitsky
Date: Wed Jul 8 14:57:31 2020 +0300
kvm: x86: replace kvm_spec_ctrl_test_value with runtime test on the host
# git
@Christian,
Yes. This following patch fixes the problem
https://lists.gnu.org/archive/html/qemu-devel/2021-03/msg01020.html
I saw your ping on the patch. I am not sure why it is not picked up. I am going
ping them today.
>If I might ask - how does the kernel fix you referenced interact with
86: Add missing cpu feature bits in EPYC-Rome
> model
>
> On Wed, Mar 3, 2021 at 5:24 PM wrote:
> >
> > On Wednesday, 2021-03-03 at 09:45:30 -06, Babu Moger wrote:
> >
> > > Found the following cpu feature bits missing from EPYC-Rome model.
> > > ibrs
6:08 AM Daniel P. Berrangé
>>> wrote:
>>>> CC'ing Babu Moger who aded the Milan CPU model.
>>>>
>>>> On Sat, Jan 29, 2022 at 07:23:37AM -0300, Leonardo Bras wrote:
>>>>> While trying to bring a VM with EPYC-Milan cpu on a host with
>>>>
t;)
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 4 +++-
target/i386/cpu.c | 18 ++
target/i386/cpu.h | 1 +
3 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 188bc9d0f8..624d
in the future. Setting this bit will also cause
CPUID validation failures when running SEV-SNP guests.
Signed-off-by: Michael Roth
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 118 +
1 file changed, 118 insertions(+)
diff --git a/target/i386
2022
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 24
target/i386/cpu.h |8
2 files changed, 32 insertions(+)
diff
to be specified for a new CPU version.
Co-developed-by: Wei Huang
Signed-off-by: Wei Huang
Signed-off-by: Michael Roth
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target
/TechDocs/40332_4.05.pdf
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 70 +
1 file changed, 70 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e9175da92f..54549a5127 100644
--- a/target/i386/cpu.c
+++ b/target/i386
tive-store-forwarding.pdf
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Signed-off-by: Babu Moger
---
target/i386/cpu.c |4 ++--
target/i386/cpu.h |4
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
This series adds following changes.
a. Allow versioned CPUs to specify new cache_info pointers.
b. Add EPYC-v4, EPYC-Rome-v3 and EPYC-Milan-v2 fixing the
cache_info.complex_indexing.
c. Introduce EPYC-Milan-v2 by adding few missing feature bits.
---
Babu Moger (3):
target/i386: Add
Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link:
https://www.amd.com/system/files/documents/security-analysis-predictive-store
IBRS.
It is a "set-and-forget" feature that means that, unlike e.g.,
s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation
resources automatically across CPL transitions.
Signed-off-by: Babu Moger
---
target/i3
to be specified for a new CPU version.
Co-developed-by: Wei Huang
Signed-off-by: Wei Huang
Signed-off-by: Michael Roth
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
---
target/i386/cpu.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git
eft always on.
The documentation for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
Revision B1 Processors
b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
Link:
https://w
in the future. Setting this bit will also cause
CPUID validation failures when running SEV-SNP guests.
Signed-off-by: Michael Roth
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
---
target/i386/cpu.c | 118 ++
1 file changed, 118 insertions(+)
diff
chitecture Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Signed-off-by: Santosh Shukla
Signed-off-by: Kim Phillips
Signed-off-by: Babu Moger
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/file
2022
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
---
target/i386/cpu.c | 24
target/i386/cpu.h | 8
2 files changed
ASE to NULL_SEL_CLR_BASE to
match the kernel name.
https://lore.kernel.org/kvm/20221205233235.622491-3-kim.phill...@amd.com/
v1:
https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit@bmoger-ubuntu/
v2: https://lore.kernel.org/kvm/20230106185700.28744-1-babu.mo...@amd.com/
G
c. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link:
https://www.amd.com/system/files/documents/securit
eft always on.
The documentation for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
Revision B1 Processors
b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
Link:
https://w
2022
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
---
target/i386/cpu.c | 24
target/i386/cpu.h | 8
2 files changed
IBRS.
It is a "set-and-forget" feature that means that, unlike e.g.,
s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation
resources automatically across CPL transitions.
Signed-off-by: Babu Moger
---
target/i3
SE to
match the kernel name.
https://lore.kernel.org/kvm/20221205233235.622491-3-kim.phill...@amd.com/
v1:
https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit@bmoger-ubuntu/
v2: https://lore.kernel.org/kvm/20230106185700.28744-1-babu.mo...@amd.com/
v3: https://lore.kernel.org/k
in the future. Setting this bit will also cause
CPUID validation failures when running SEV-SNP guests.
Signed-off-by: Michael Roth
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
---
target/i386/cpu.c | 118 ++
1 file changed, 118 insertions(+)
diff
Definition",
to allow new cache_info pointers to be specified for a new CPU version.
Co-developed-by: Wei Huang
Signed-off-by: Wei Huang
Signed-off-by: Michael Roth
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
---
target/i386/cpu.c | 35 ---
1 f
chitecture Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Signed-off-by: Santosh Shukla
Signed-off-by: Kim Phillips
Signed-off-by: Babu Moger
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/file
t;)
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
Reviewed-by: Zhao Liu
---
v2: Rebased to the latest tree.
Updated the pc_compat_8_2 for the new flag.
Added the comment for new property legacy_multi_node.
Added Reviwed-by from Zh
t;)
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Reviewed-by: Zhao Liu
Signed-off-by: Babu Moger
---
v3:
Rebased to the latest tree.
Updated the pc_compat_9_0 for the new flag.
v2:
https://lore.kernel.org/kvm/20240102231738.46553-1-babu.mo...@amd.com/
Rebased to the latest t
to determine
the number of available counters for different PMUs. It also denotes the
availability of global control and status registers.
Add the required CPUID feature word and feature bit to allow guests to
make use of the PerfMonV2 features.
Signed-off-by: Sandipan Das
Signed-off-by: Babu Moger
avx512-vp2intersect: AVX512 Vector Pair Intersection to a Pair
of Mask Register
avx-vnni : AVX VNNI Instruction
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 131 ++
1 file changed, 131 insertions(+)
diff --git a/target
interrupts.
McaOverflowRecov: MCA overflow recovery support.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 165b982c8c..86a90b1405 100644
--- a/target/i386/cpu.c
+++ b
.
Signed-off-by: Babu Moger
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
---
target/i386/cpu.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7f1837cdc9..64e6dc62e2 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
This series adds the support for following features in qemu.
1. RAS feature bits (SUCCOR, McaOverflowRecov)
2. perfmon-v2
3. Update EPYC-Genoa to support perfmon-v2 and RAS bits
4. Add support for EPYC-Turin
Babu Moger (3):
i386/cpu: Add RAS feature bits on EPYC CPU models
i386/cpu: Enable
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