Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa
extension.
However, it has some typos for fleq.d and fltq.d. Both of them misused the
fltq.s
helper function.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvzfa.c.inc | 4 ++--
1 file
Commit bef6f008b98(accel/tcg: Return bool from page_check_range) converts
integer return value to bool type. However, it wrongly converted the use
of the API in riscv fault-only-first, where page_check_range < = 0, should
be converted to !page_check_range.
Signed-off-by: LIU Zhiwei
---
tar
On 2023/7/30 5:18, Richard Henderson wrote:
On 7/28/23 20:16, LIU Zhiwei wrote:
Commit bef6f008b98(accel/tcg: Return bool from page_check_range)
converts
integer return value to bool type. However, it wrongly converted the use
of the API in riscv fault-only-first, where page_check_range
On 2024/2/29 2:51, Atish Patra wrote:
Privilege mode filtering can also be emulated for cycle/instret by
tracking host_ticks/icount during each privilege mode switch. This
patch implements that for both cycle/instret and mhpmcounters. The
first one requires Smcntrpmf while the other one require
On 2024/2/29 2:51, Atish Patra wrote:
From: Kaiwen Xue
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 ins
: Alistair Francis
Reviewed-by: LIU Zhiwei
Zhiwei
Signed-off-by: Atish Patra
---
target/riscv/csr.c | 67 ++
1 file changed, 38 insertions(+), 29 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d4e8ac13b90c..a3d979c4c72c 10
The real return value type has been converted to RISCVException,
but some function declarations still not. This patch makes all
csr operation declarations use RISCVExcetion.
Signed-off-by: LIU Zhiwei
---
target/riscv/csr.c | 117 -
1 file changed, 74
vxrm and vxsat have been moved into a special register vcsr since
RVV v1.0. So remove them from FCSR for vector 1.0.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 8
1 file changed, 8 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index
riscv specification allows custom CSRs in decode area. So we should
register all vendor CSRs in cpu realize stage.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 3 +++
target/riscv/tcg/tcg-cpu.c | 26 ++
target/riscv/tcg/tcg-cpu.h | 1 +
3 files changed
We first add a framework for vendor CSRs in patch 1. After that we add
one thead-c906 CSR mxstatus, which is used for mmu extension xtheadmaee.
This patch set fix the regression on kernel pointed by Björn Töpel in
https://www.mail-archive.com/qemu-devel@nongnu.org/msg1018232.html.
LIU Zhiwei (2
The sections "5.2.2.1 Page table structure" and "15.1.7.1 M-mode extension
status register (MXSTATUS)" in document[1] give the detailed information
about its design.
[1]:https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699265191641/XuanTie-Openc906-UserManual.pdf
On 2024/1/31 13:06, Richard Henderson wrote:
On 1/30/24 21:11, LIU Zhiwei wrote:
+/* This stub just works for making vendors array not empty */
+riscv_csr_operations stub_csr_ops[CSR_TABLE_SIZE];
+static inline bool never_p(const RISCVCPUConfig *cfg)
+{
+ return false;
+}
+
+void
On 2024/1/31 13:07, Richard Henderson wrote:
On 1/30/24 21:11, LIU Zhiwei wrote:
+riscv_csr_operations th_csr_ops[CSR_TABLE_SIZE] = {
+#if !defined(CONFIG_USER_ONLY)
+ [CSR_TH_MXSTATUS] = { "th_mxstatus", th_maee_check,
read_th_mxstatus,
+ write_th_mxstatus
b.com/T-head-Semi/thead-extension-spec/blob/master/xtheadmaee.adoc
LIU Zhiwei (2):
target/riscv: Register vendors CSR
target/riscv: Support xtheadmaee for thead-c906
target/riscv/cpu.c | 9 ++
target/riscv/cpu.h | 9 ++
target/riscv/cpu_bits.h| 6
target/
riscv specification allows custom CSRs in decode area. So we should
register all vendor CSRs in cpu realize stage.
Signed-off-by: LIU Zhiwei
---
1) Use int index to quiet the Werror for "i < 0".
---
target/riscv/cpu.c | 3 +++
target/riscv/tcg/tcg-cpu.c | 18 +
re as
xtheadmaee[1]. this feature is controlled by an custom CSR named mxstatus,
whose maee field encodes whether enable the pte [60-63] bits.
[1]:https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadmaee.adoc
Signed-off-by: LIU Zhiwei
---
v1->v2:
1) Remove mxstatus user mode acces
On 2024/1/30 19:43, Christoph Müllner wrote:
On Tue, Jan 30, 2024 at 12:12 PM LIU Zhiwei
wrote:
thead-c906 uses some flags in pte [60-63] bits. It has history reasons that
SVPBMT didn't exist when thead-c906 came to world.
We named this feature as xtheadmaee. this feature is controll
/sync_i.adoc
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_xthead.c.inc | 10 --
1 file changed, 10 deletions(-)
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc
b/target/riscv/insn_trans/trans_xthead.c.inc
index dbb6411239..22488412d4 100644
--- a/target/riscv/insn_trans
d blocks */
+#endif
Reviewed-by: LIU Zhiwei
Zhiwei
memset(base + cnt, -1, tot - cnt);
}
};
+
+void th_register_custom_csrs(RISCVCPU *cpu)
+{
+for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
+int csrno = th_csr_list[i].csrno;
+riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
+ if (!th_csr_list[i].insertion_test(cpu))
+riscv_set_csr_ops(csrno, csr_ops);
+}
+}
Otherwise,
Reviewed-by: LIU Zhiwei
Zhiwei
Hi Daniel and Alistair,
Hope it is not too late. I think there are two bugs in this patch.
1) The first is for instruction vfmv.s.f. vfmv.s.f doesn't use helper
function. If we remove the over check, it will set the first element of
destination vector register, which is against the specificat
On 2024/3/10 4:43, Daniel Henrique Barboza wrote:
Change all code that updates tail elems to use vext_set_tail_elems_1s()
instead of vext_set_elems_1s().
Hi Daniel,
Notice vext_set_tail_elems_1s will use NF field, which is zero for most
vector instructions. Thus it will do nothing.
I think
On 2024/3/12 2:08, Daniel Henrique Barboza wrote:
The previous patch added an early vstart >= vl exit in all vector
helpers, most of them using the VSTART_CHECK_EARLY_EXIT() macro,
and now we're left with a lot of 'brcond' that has not use. The
pattern goes like this:
VSTART_CHECK_EARLY_E
, ret, GETPC());
Hi Yu-Ming,
The 128-bit CSR operations have the similar errors. Could you solve the
similar bug in this patch set?
Otherwise,
Reviewed-by: LIU Zhiwei
Thanks,
Zhiwei
Francis
Reviewed-by: LIU Zhiwei
Zhiwei
---
target/riscv/vector_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index fe56c007d5..ca79571ae2 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@
potential 'over' brconds, and that will also
mandate a mark_vs_dirty() too.
Fixes: dedc53cbc9 ("target/riscv: rvv-1.0: integer scalar move instructions")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewd-by: LIU Zhiwei
Zhiwei
---
target/ri
memcpy((uint8_t *)vd + H1(j - 1),
+ (uint8_t *)vs2 + H1(j - 1),
+ j - i);
+i = j;
+}
+
memcpy((uint8_t *)vd + H1(i),
(uint8_t *)vs2 + H1(i),
- maxsz - startb);
+ maxsz - i);
Reviewed-by: LIU Zhiwei
Zhiwei
env->vstart = 0;
}
', and clear vstart if that
happens.
This way we're now sure that vstart is being cleared in the end of the
execution, regardless of the path taken.
Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: L
*ctx, arg_ebreak *a)
if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
} else {
+tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+ offsetof(CPURISCVState,
rue;
}
} else {
/* check U/S/M bit against current privilege level */
if ((ctrl >> 3) & BIT(env->priv)) {
+env->badaddr = pc;
return true;
}
}
Reviewed-by: LIU Zhiwei
Zhiwei
_cpu_extensions[] = {
/* Vector cryptography extensions */
MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
Revi
Hi, Alistair
On 2020/2/19 6:34, Alistair Francis wrote:
On Mon, Feb 10, 2020 at 12:12 AM LIU Zhiwei wrote:
Vector extension is default on only for "any" cpu. It can be turned
on by command line "-cpu rv64,v=true,vlen=128,elen=64,vext_spec=v0.7.1".
vlen is the vector regi
Hi, Richard
Thanks for your informative comments. I'm addressing these comments.
And a little confused in some comments.
On 2020/2/12 14:38, Richard Henderson wrote:
On 2/9/20 11:42 PM, LIU Zhiwei wrote:
+/*
+ * As simd_desc supports at most 256 bytes, and in this implementation,
+ * th
PC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (4):
target/riscv: add vector extension field in CPURISCVState
target/riscv: implementation-defined constant parameters
target/riscv: support vector extension csr
target/riscv: add vector configure instruction
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 75 -
2 files
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 7 +++
target/riscv/cpu.h | 5 +
2 files changed, 12 insertions(+)
diff --git a
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 12
1
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
---
MAI
rd working on DSP extension, and
send the
> first patch in middle October.
>
> Could the maintainers tell me whether the specs referenced are
> appropriate? Is anyone working on these extensions? I'd like to get
> your status, and maybe discuss questions and work togather.
>
> Best Regards
>
> LIU Zhiwei
>
>
>
>
ery
useful, but everyone is busy with something at the moment
unfortunately.
Alistair
Best Regards
LIU Zhiwei
.
V2
* use float16_compare{_quiet}
* only use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (5):
target/riscv: add vector unit stride load and store instructions
target/riscv: add vector stride load and store instructions
target/riscv: add vector index load and store
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 35
target/riscv/insn32.decode
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h
: LIU Zhiwei
---
target/riscv/helper.h | 70
target/riscv/insn32.decode | 17 +
target/riscv/insn_trans/trans_rvv.inc.c | 294
target/riscv/translate.c| 2 +
target/riscv/vector_helper.c| 438
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 35
ck for vector register description.
V2
* use float16_compare{_quiet}
* only use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (4):
target/riscv: add vector extension field in CPURISCVState
target/riscv: configure and turn on vector extension from command line
target/r
t_spec is the vector specification version, default value is v0.7.1.
Thest properties and cpu can be specified with other values.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 48 --
target/riscv/cpu.h | 8
2 files changed, 54 insertions(+),
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno,offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 13 +
1
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 72 +++--
2 files
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
---
MAI
On 2020/2/11 23:53, Richard Henderson wrote:
On 2/10/20 8:12 AM, LIU Zhiwei wrote:
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno,offset).
Thus elements can be directly accessed by offset from the first vector
On 2020/2/11 23:56, Richard Henderson wrote:
On 2/10/20 8:12 AM, LIU Zhiwei wrote:
+if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
+error_setg(errp,
+ "Vector extension implementation o
On 2020/2/12 0:11, Richard Henderson wrote:
On 2/10/20 8:12 AM, LIU Zhiwei wrote:
+static int vs(CPURISCVState *env, int csrno)
+{
+return 0;
+}
This should at least be testing RVV, a-la smode().
Testing RVV is ok.
I'm not quite understand "a -1a smode()" here. Coul
On 2020/2/12 0:56, Richard Henderson wrote:
On 2/10/20 8:12 AM, LIU Zhiwei wrote:
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-target_ulong *cs_base, uint32_t *flags
Hi, Richard
Thanks for comments.
On 2020/2/12 14:38, Richard Henderson wrote:
On 2/9/20 11:42 PM, LIU Zhiwei wrote:
+/*
+ * As simd_desc supports at most 256 bytes, and in this implementation,
+ * the max vector group length is 2048 bytes. So split it into two parts.
+ *
+ * The first part is
We have found two places that misuse the fields from env.
The patch set fixes two of them. The first is virt_enabled. And another is
vstart.
And for easy moving the tb flag fields, I also make the FS and VS in tb flags
positions changable.
LIU Zhiwei (4):
target/riscv: Extract virt enabled
On 2023/3/24 20:53, liweiwei wrote:
On 2023/3/24 13:59, LIU Zhiwei wrote:
The pointer masking is the only extension that directly use status.
The vector or float extension uses the status in an indirect way.
Replace the pointer masking extension special status fields with
the general status
Once we mistook the vstart directly from the env->vstart. As env->vstart is not
a constant, we should record it in the tb flags if we want to use
it in translation.
Reported-by: Richard Henderson
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h
Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a normal
way.
It will make us change the tb flags layout difficult. And even worse, if we
want to keep tb flags for a same extension togather without a hole.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h
The pointer masking is the only extension that directly use status.
The vector or float extension uses the status in an indirect way.
Replace the pointer masking extension special status fields with
the general status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 2 +-
target/riscv
Virt enabled state is not a constant. So we should put it into tb flags.
Thus we can use it like a constant condition at translation phase.
Reported-by: Richard Henderson
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_helper.c | 2 ++
target/riscv
structions.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_privileged.c.inc | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc
b/target/riscv/insn_trans/trans_privileged.c.inc
index 59501b2780..e3bee971c6 100644
--- a/target/riscv/
On 2023/3/24 20:38, Weiwei Li wrote:
Fix identation problems, and try to use the same indentation strategy
in the same file.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/arch_dump.c| 4 +-
target/riscv/cpu.c | 4 +-
targe
Currently we only use the env->virt to encode the virtual mode enabled
status. Let's make it a bool type.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h| 2 +-
target/riscv/cpu_bits.h | 3 ---
target/riscv/cpu_helper.c | 6 +++---
target/riscv/machine.c| 6 +++---
targ
the riscv_cpu_virt_enabled
which has been called so many times.
you can pick it up into this patch set if you desire.
No matter what you choose, after small fix for patch 6, for this whole
patch set
Reviewed-by: LIU Zhiwei
Zhiwei
The port is available here:
https://github.com/plctlab/plct-qemu/t
On 2023/3/25 18:54, Richard Henderson wrote:
Use the priv level encoded into the mmu_idx, rather than
starting from env->priv. We have already checked MPRV+MPP
in riscv_cpu_mmu_index -- no need to repeat that.
Signed-off-by: Richard Henderson
---
target/riscv/internals.h | 9 +
t
On 2023/3/27 16:08, Weiwei Li wrote:
Directly use env->virt_enabled instead.
Suggested-by: LIU Zhiwei
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c| 2 +-
target/riscv/cpu.h| 1 -
target/riscv/cpu_helper.c |
On 2023/3/28 0:29, Richard Henderson wrote:
On 3/26/23 19:07, LIU Zhiwei wrote:
+static inline int mmuidx_priv(int mmu_idx)
+{
+ int ret = mmu_idx & 3;
+ if (ret == MMUIdx_S_SUM) {
+ ret = PRV_S;
+ }
+ return ret;
+}
+
Can we remove the PRIV from the tb flags afte
On 2023/3/28 9:33, LIU Zhiwei wrote:
On 2023/3/28 0:29, Richard Henderson wrote:
On 3/26/23 19:07, LIU Zhiwei wrote:
+static inline int mmuidx_priv(int mmu_idx)
+{
+ int ret = mmu_idx & 3;
+ if (ret == MMUIdx_S_SUM) {
+ ret = PRV_S;
+ }
+ return ret;
+}
+
Can we re
On 2023/3/27 18:00, Weiwei Li wrote:
Currently, the pc use signed-extend(in gen_set_pc*) when xl = 32. And
data address should use the same memory address space with it when
xl = 32. So we should change their address calculation to use sign-extended
address when xl = 32.
Incorrect. PC sign-ext
On 2023/3/27 18:00, Weiwei Li wrote:
Since pointer mask works on effective address, and the xl works on the
generation of effective address, so xl related calculation should be done
before pointer mask.
Incorrect. It has been done.
When updating the pm_mask, we have already considered the e
*env, target_ulong addr)
{
-return (addr & env->cur_pmmask) | env->cur_pmbase;
+return (addr & ~env->cur_pmmask) | env->cur_pmbase;
It's my typo. Thanks.
Reviewed-by: LIU Zhiwei
Zhiwei
}
/*
On 2023/3/27 18:00, Weiwei Li wrote:
Sign-extend the vector address when xl = 32.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/vector_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index
On 2023/3/28 9:55, liweiwei wrote:
On 2023/3/28 02:04, Richard Henderson wrote:
On 3/27/23 03:00, Weiwei Li wrote:
@@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr
address, int size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d
mmu_idx %d\n",
On 2023/3/25 18:54, Richard Henderson wrote:
Merge with mstatus_{fs,vs}. We might perform a redundant
assignment to one or the other field, but it's a trivial
and saves 4 bits from TB_FLAGS.
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Zhiwei
---
target/riscv/
dx & TB_FLAGS_PRIV_MMU_MASK;
-#endif
+return ctx->priv;
}
Could you remove the priv_level and use ctx->priv directly in this file
Otherwise,
Reviewed-by: LIU Zhiwei
Zhiwei
/* Test if priv level is M, S, or U (cannot fail). */
s.h"
+/*
+ * The current MMU Modes are:
+ * - U 0b000
+ * - S 0b001
+ * - S+SUM 0b010
+ * - M 0b011
+ * - HLV/HLVX/HSV adds 0b100
Reviewed-by: LIU Zhiwei
Zhiwei
+ */
+#define MMUIdx_U0
+#define MMUIdx_S
On 2023/3/28 11:18, Richard Henderson wrote:
On 3/27/23 19:48, liweiwei wrote:
On 2023/3/28 10:20, LIU Zhiwei wrote:
On 2023/3/27 18:00, Weiwei Li wrote:
Since pointer mask works on effective address, and the xl works on the
generation of effective address, so xl related calculation
On 2023/3/28 11:33, liweiwei wrote:
On 2023/3/28 11:18, Richard Henderson wrote:
On 3/27/23 19:48, liweiwei wrote:
On 2023/3/28 10:20, LIU Zhiwei wrote:
On 2023/3/27 18:00, Weiwei Li wrote:
Since pointer mask works on effective address, and the xl works on
the
generation of effective
mpute_xl(env);
+riscv_cpu_update_mask(env);
+}
Reviewed-by: LIU Zhiwei
Zhiwei
return RISCV_EXCP_NONE;
}
te.c
@@ -551,6 +551,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong
imm)
next_pc = ctx->base.pc_next + imm;
if (!has_ext(ctx, RVC)) {
if ((next_pc & 0x3) != 0) {
+gen_set_pc_imm(ctx, next_pc);
I think this patch is better than it in v
*dev, Error
**errp)
#ifndef CONFIG_USER_ONLY
+cs->tcg_cflags |= CF_PCREL;
+
Reviewed-by: LIU Zhiwei
Zhiwei
if (cpu->cfg.ext_sstc) {
riscv_timer_init(cpu);
}
On 2023/4/1 20:49, Weiwei Li wrote:
Add a base save_pc For
pc_save for
PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated from tb related pc:
real_pc = (old)env->pc + target_pc(from tb) - ctx->save_p
On 2023/4/2 16:17, liweiwei wrote:
On 2023/4/2 08:34, LIU Zhiwei wrote:
On 2023/4/1 20:49, Weiwei Li wrote:
Add a base save_pc For
pc_save for
PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated
On 2023/4/1 20:49, Weiwei Li wrote:
Add a base save_pc For PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated from tb related pc:
real_pc = (old)env->pc + target_pc(from tb) - ctx->save_pc
Use gen_get_
On 2023/4/4 10:13, liweiwei wrote:
On 2023/4/4 09:58, LIU Zhiwei wrote:
On 2023/4/1 20:49, Weiwei Li wrote:
Add a base save_pc For PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated from tb relat
2b64129 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3518,8 +3518,6 @@ static RISCVException write_mmte(CPURISCVState *env, int
csrno,
/* for machine mode pm.current is hardwired to 1 */
wpri_val |= MMTE_M_PM_CURRENT;
-/* hardwiring pm.instruction bit to 0, since it'
On 2023/4/4 10:06, Weiwei Li wrote:
Compute the target address before storing it into badaddr
when mis-aligned exception is triggered.
Use a target_pc temp to store the target address to avoid
the confusing operation that udpate target address into
cpu_pc before misalign check, then update it i
On 2023/4/4 10:06, Weiwei Li wrote:
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
We can get pc-relative address from following formula:
real_pc = (old)env->pc + diff, where diff = target_pc - ctx->pc_save.
Use
On 2023/4/4 11:12, LIU Zhiwei wrote:
On 2023/4/4 10:06, Weiwei Li wrote:
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
We can get pc-relative address from following formula:
real_pc = (old)env->pc + d
On 2023/4/4 11:46, liweiwei wrote:
On 2023/4/4 11:12, LIU Zhiwei wrote:
On 2023/4/4 10:06, Weiwei Li wrote:
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
We can get pc-relative address from following formula
et/riscv: Reduce overhead of MSTATUS_SUM change
LIU Zhiwei (4):
target/riscv: Extract virt enabled state from tb flags
target/riscv: Add a general status enum for extensions
target/riscv: Encode the FS and VS on a normal way for tb flags
target/riscv: Add a tb flags field for vsta
On 2023/4/4 16:48, liweiwei wrote:
On 2023/4/4 15:07, LIU Zhiwei wrote:
On 2023/4/4 11:46, liweiwei wrote:
On 2023/4/4 11:12, LIU Zhiwei wrote:
On 2023/4/4 10:06, Weiwei Li wrote:
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by
On 2023/4/1 2:28, Christoph Muellner wrote:
From: Christoph Müllner
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point extensions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* froun
On 2023/1/25 4:44, Richard Henderson wrote:
On 1/24/23 09:59, Christoph Muellner wrote:
+static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp
memop,
+ int shamt)
+{
+ TCGv rd1 = dest_gpr(ctx, a->rd1);
+ TCGv rd2 = dest_gpr(ctx, a->rd2);
+ TC
On 2023/1/30 13:43, Richard Henderson wrote:
On 1/29/23 16:03, LIU Zhiwei wrote:
Thanks. It's a bug. We should load all memory addresses to local TCG
temps first.
Do you think we should probe all the memory addresses for the store
pair instructions? If so, can we avoid the use of a h
On 2023/1/25 5:21, Richard Henderson wrote:
On 1/24/23 09:59, Christoph Muellner wrote:
+/* XTheadMemIdx */
+
+/*
+ * Load with memop from indexed address and add (imm5 << imm2) to rs1.
+ * If !preinc, then the load address is rs1.
+ * If preinc, then the load address is rs1 + (imm5) << imm2)
On 2023/1/25 5:26, Richard Henderson wrote:
On 1/24/23 09:59, Christoph Muellner wrote:
+++ b/target/riscv/cpu.h
@@ -27,6 +27,7 @@
#include "qom/object.h"
#include "qemu/int128.h"
#include "cpu_bits.h"
+#include "cpu_vendorid.h"
I don't see that this ID is required for all users of ris
On 2023/1/31 3:03, Richard Henderson wrote:
On 1/29/23 22:41, LIU Zhiwei wrote:
On 2023/1/30 13:43, Richard Henderson wrote:
On 1/29/23 16:03, LIU Zhiwei wrote:
Thanks. It's a bug. We should load all memory addresses to local
TCG temps first.
Do you think we should probe all the m
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