> > I meant TLB change by e.g. tlb_set_page. If you change single page
> > mapping then all TBs in that page will be gone.
> > This may be the result of e.g. a page swapping, or a task switch.
>
> You said "all TBs in that page will be gone". Does it mean QEMU will
> invalidate those TBs by for
> Sorry, I have to be sure what you talked about is guest or host.
> Let me try.
>
>> Well, my explanation sucks. Let's say it other way, more precisely:
>> - you have two pieces of code in different pages, one of them jumps to the
>> other;
>
> guest code in different guest pages.
Right.
>> -
> I am not sure when/where __stl_mmu/__ldl_mmu are used. I do set
They are called from the places in TBs where
tcg_gen_qemu_{ld,st}{8,16,32,64}{u,s} were injected.
> breakpoint on __stl_mmu/__ldl_mmu, but the backtrace can only show
> something like,
>
> #0 __stl_mmu (addr=196608, val=0, mmu_idx
> > They are called from the places in TBs where
> > tcg_gen_qemu_{ld,st}{8,16,32,64}{u,s} were injected.
>
> So you mean __stl_mmu/__ldl_mmu are called from the code cache.
>
> > > breakpoint on __stl_mmu/__ldl_mmu, but the backtrace can only show
> > > something like,
> > >
> > > #0 鍮_stl_mm
: Max Filippov
---
hw/xtensa_pic.c | 27 ++-
target-xtensa/cpu.h |1 +
target-xtensa/op_helper.c | 18 ++--
tests/xtensa/test_timer.S | 63 +
4 files changed, 93 insertions(+), 16 deletions(-)
diff --git
Signed-off-by: Max Filippov
---
qemu-doc.texi | 55 +++
qemu-tech.texi | 40 +---
2 files changed, 88 insertions(+), 7 deletions(-)
diff --git a/qemu-doc.texi b/qemu-doc.texi
index 31199f6..ad19b73
Signed-off-by: Max Filippov
---
tests/xtensa/Makefile |1 +
tests/xtensa/test_mac16.S | 243 +
2 files changed, 244 insertions(+), 0 deletions(-)
create mode 100644 tests/xtensa/test_mac16.S
diff --git a/tests/xtensa/Makefile b/tests/xtensa
See ISA, 4.3.7 for the details.
- add ACC and MR special registers;
- implement MAC16 and all inner MAC* opcode groups.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |3 +
target-xtensa/translate.c | 135 -
2 files changed, 137
Max Filippov (2):
target-xtensa: implement MAC16 option
target-xtensa: add MAC16 unit tests
target-xtensa/cpu.h |3 +
target-xtensa/translate.c | 135 +-
tests/xtensa/Makefile |1 +
tests/xtensa/test_mac16.S | 243
/DIP switches access.
Signed-off-by: Max Filippov
---
Makefile.target |1 +
default-configs/xtensa-softmmu.mak |3 +
default-configs/xtensaeb-softmmu.mak |3 +
hw/xtensa_lx60.c | 232 ++
4 files changed, 239
This is OpenCores Ethernet MAC + subset of National Semiconductors
DP83838C PHY.
OpenCores Ethernet MAC project: http://opencores.org/project,ethmac
Signed-off-by: Max Filippov
---
Makefile.objs |1 +
hw/opencores_eth.c | 728
trace
Max Filippov (2):
hw: add OpenCores 10/100 Mbps Ethernet controller
target-xtensa: add Avnet LX60/LX110/LX200 boards
Makefile.objs|1 +
Makefile.target |1 +
default-configs/xtensa-softmmu.mak |3 +
default-configs/xtensaeb
This is to get aligned with the linux name for this machine.
Signed-off-by: Max Filippov
---
Makefile.target |2 +-
hw/xtensa_dc232b.c| 116 -
hw/xtensa_sim.c | 116 +
tests
- add separate options for each operation in the MISC_OP;
- add an option for MULSH/MULUH;
- put S32C1I under conditional store option.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |6 +-
target-xtensa/translate.c | 14 +++---
2 files changed, 12 insertions(+), 8
Max Filippov (7):
target-xtensa: increase xtensa options accuracy
target-xtensa: remove hand-written xtensa cores implementations
target-xtensa: implement external interrupt mapping
target-xtensa: extract core configuration from overlay
target-xtensa: add dc232b core
target-xtensa: add
overlay_tool.h
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |6 +
target-xtensa/helper.c | 27 ++-
target-xtensa/overlay_tool.h | 533 ++
3 files changed, 553 insertions(+), 13 deletions(-)
create mode 100644 target-xtensa/overlay_tool.h
This is FSF big endian core implemented through linux/gdb overlay.
Signed-off-by: Max Filippov
---
Makefile.target |1 +
target-xtensa/core-fsf.c| 28 +++
target-xtensa/core-fsf/core-isa.h | 362 +++
target-xtensa/core-fsf
This is Diamond 232L Standard Core Rev.B (LE), implemented through
linux/gdb overlay.
Signed-off-by: Max Filippov
---
Makefile.target|1 +
target-xtensa/core-dc232b.c| 28 ++
target-xtensa/core-dc232b/core-isa.h | 424
Xtensa cores may have different mapping of external interrupt pins to
internal IRQ numers. Implement API to acquire core IRQ by its external
interrupt number.
Signed-off-by: Max Filippov
---
hw/xtensa_pic.c | 12
target-xtensa/cpu.h |3 +++
2 files changed, 15 insertions
Signed-off-by: Max Filippov
---
Makefile.target |1 -
hw/xtensa_sample.c| 107 ---
target-xtensa/gdb-config-dc232b.c | 261 -
target-xtensa/gdb-config-sample-xtensa-core.c | 375
Signed-off-by: Max Filippov
---
v1 -> v2 change: fix menu item text in qemu-tech.texi
---
qemu-doc.texi | 55 +++
qemu-tech.texi | 40 +---
2 files changed, 88 insertions(+), 7 deletions(-)
diff --gi
> For any major feature that you're targeting to the next release, you should:
>
> # Make sure that you've posted a patch series to qemu-devel
> # Write a Feature page on the qemu.org wiki describing the feature and the
> motivation
> # On the release planning wiki page, link to your feature wiki p
> I've read a few days ago that it was possible to emulate PCI device with
> 64-bit BARs and have a real 64-bit memory access.
> Thus, I've created a virtual device named toto accessible through a 64-bit
> BAR
You've probably confused an ability to locate BAR anywhere in 64-bit
address space (s
> > diff --git a/target-xtensa/core-fsf/gdb-config.c
> > b/target-xtensa/core-fsf/gdb-config.c
> > new file mode 100644
> > index 000..6705d9c
> > --- /dev/null
> > +++ b/target-xtensa/core-fsf/gdb-config.c
> > @@ -0,0 +1,152 @@
> > +/* Configuration for the Xtensa architecture for GDB, the GN
> > Nack. GPLv3 is by design incompatible with GPLv2only (but not with
> > GPLv2+ or IIRC BSD-like) licenses. Please only use code from GDB
> > before v3 switch.
>
> Ok, let's drop this patch. Fortunately nothing really depends on it.
> I could re-format xtensa-config.c from gdb-6.6, but register
This is FSF big endian core implemented through linux/gdb overlay.
Signed-off-by: Max Filippov
---
v1 -> v2 change: remove GDB register definitions due to their GPL3 license
---
Makefile.target |1 +
target-xtensa/core-fsf.c | 22 +++
target-xtensa/core-
> On Mon, Oct 10, 2011 at 2:25 AM, Max Filippov wrote:
> > Max Filippov (7):
> > target-xtensa: increase xtensa options accuracy
> > target-xtensa: remove hand-written xtensa cores implementations
> > target-xtensa: implement external interrupt mapping
>
> On Mon, Oct 10, 2011 at 2:27 AM, Max Filippov wrote:
> > Max Filippov (2):
> > hw: add OpenCores 10/100 Mbps Ethernet controller
> > target-xtensa: add Avnet LX60/LX110/LX200 boards
>
> These patches depend on the 7-patch series. Please mention if the
> patch s
- add separate options for each operation in the MISC_OP;
- add an option for MULSH/MULUH;
- put S32C1I under conditional store option.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |6 +-
target-xtensa/translate.c | 14 +++---
2 files changed, 12 insertions(+), 8
Xtensa cores may have different mapping of external interrupt pins to
internal IRQ numers. Implement API to acquire core IRQ by its external
interrupt number.
Signed-off-by: Max Filippov
---
hw/xtensa_pic.c | 12
target-xtensa/cpu.h |3 +++
2 files changed, 15 insertions
Max Filippov (7):
target-xtensa: increase xtensa options accuracy
target-xtensa: remove hand-written xtensa cores implementations
target-xtensa: implement external interrupt mapping
target-xtensa: extract core configuration from overlay
target-xtensa: add dc232b core
target-xtensa: add
This is FSF big endian core implemented through linux overlay.
Signed-off-by: Max Filippov
---
v1 -> v2 changes:
- remove GDB register definitions due to their GPL3 license;
- fix stylistical issues in core-isa.h
---
Makefile.target |1 +
target-xtensa/core-fs
Signed-off-by: Max Filippov
---
Makefile.target |1 -
hw/xtensa_sample.c| 107 ---
target-xtensa/gdb-config-dc232b.c | 261 -
target-xtensa/gdb-config-sample-xtensa-core.c | 375
/DIP switches access.
Signed-off-by: Max Filippov
---
v1 -> v2 changes: adopt serial_mm_init converted to new memory API
---
Makefile.target |1 +
default-configs/xtensa-softmmu.mak |3 +
default-configs/xtensaeb-softmmu.mak |3 +
hw/xtensa_lx6
This is OpenCores Ethernet MAC + subset of National Semiconductors
DP83838C PHY.
OpenCores Ethernet MAC project: http://opencores.org/project,ethmac
Signed-off-by: Max Filippov
---
Makefile.objs |1 +
hw/opencores_eth.c | 728
trace
Please apply it after 'target-xtensa: add overlay parsing header' series.
Max Filippov (2):
hw: add OpenCores 10/100 Mbps Ethernet controller
target-xtensa: add Avnet LX60/LX110/LX200 boards
Makefile.objs|1 +
Makefile.target
This is Diamond 232L Standard Core Rev.B (LE), implemented through
linux/gdb overlay.
Signed-off-by: Max Filippov
---
v1 -> v2 changes: fix stylistical issues in core-isa.h
---
Makefile.target|1 +
target-xtensa/core-dc232b.c| 28 ++
target-xtensa/c
This is to get aligned with the linux name for this machine.
Signed-off-by: Max Filippov
---
Makefile.target |2 +-
hw/xtensa_dc232b.c| 116 -
hw/xtensa_sim.c | 116 +
tests
overlay_tool.h
Signed-off-by: Max Filippov
---
v1 -> v2 changes:
- fix trailing newline in overlay_tool.h;
- only register cores that match current build target endianness.
---
target-xtensa/cpu.h |6 +
target-xtensa/helper.c | 27 ++-
target-xtensa/overlay_tool.h |
Hello.
I'm developing support for new qemu target architecture: xtensa [1],
primarily because AFAIK there's no free/open simulator for this
architecture.
Essential ISA parts (like core opcodes, special registers, windowed
registers, exceptions and interrupts) are implemented, other (like
TLB, MMU
>> Essential ISA parts (like core opcodes, special registers, windowed
>> registers, exceptions and interrupts) are implemented, other (like
>> TLB, MMU, caches, coprocessors, rare opcodes) are not, although I'm
>> planning to implement them if/when needed.
>
> Nice work. What is the status, can th
>>> - if possible, simcall should become a linux-user target instead
>>
>> simcall is used in freestanding libc provided by Tensilica, I guess
>> primarily to ease OS-less development. I can make it an additional
>> option, but it seems impractical to remove it completely.
>
> Does that still emula
>>> What is the reason for that? DisasContext itself has a pointer to env.
>>> Can it be used instead?
>>
>> DisasContext shouldn't have that pointer. Some of the decisions during
>> translation are made based on CPU model/features which don't change
>> during execution. Other decisions should be m
Signed-off-by: Max Filippov
---
configure |9 +
default-configs/xtensa-softmmu.mak |1 +
2 files changed, 10 insertions(+), 0 deletions(-)
create mode 100644 default-configs/xtensa-softmmu.mak
diff --git a/configure b/configure
index 6f75e2e..d8c33b9
Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h | 60 +++
target-xtensa
NEG and ABS are the only members of RT0 group.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 26fc28b..49f4940 100644
--- a/target
Signed-off-by: Max Filippov
---
Makefile.target |2 +
arch_init.c |2 +
arch_init.h |1 +
cpu-exec.c| 10 +
elf.h |2 +
hw/xtensa_pic.c | 11 ++
target-xtensa/cpu.h | 84
Sample board and sample CPU core are used for debug and may be used for
development of custom SoC emulators.
This board has two fixed size memory regions for DTCM and ITCM and
variable length SRAM region.
Signed-off-by: Max Filippov
---
Makefile.target|1 +
hw/xtensa_sample.c | 68
Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 57 +
1 files changed, 57 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xte
Reserved opcodes must generate illegal instruction exception. Usually
they signal emulation quality problems.
Not implemented opcodes are good to see.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 111 -
1 files changed, 110 insertions
Signed-off-by: Max Filippov
---
configure |1 +
default-configs/xtensa-softmmu.mak |1 +
gdb-xml/xtensa-core.xml| 24 ++
gdbstub.c | 39
4 files changed, 65
Group SNM0 (indirect jumps and calls).
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 49 -
1 files changed, 48 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 2bfa801..f4d74e0
All operations in this group are no-ops, because there are no delayed
side effects.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 31 ++-
1 files changed, 30 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa
- BZ (comparison to zero);
- BI0 (comparison to signed immediate);
- BI1 (comparison to unsigned immediate);
- B (two registers comparison, bit sets comparison).
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 188 +
1 files changed, 188
- ST1: SAR (shift amount special register) manipulation, NSA(U);
- RST1: shifts, 16-bit multiplication.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |4 +
target-xtensa/translate.c | 210 +
2 files changed, 214 insertions(+), 0
uregnames are considered valid.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |7 ++
target-xtensa/translate.c | 47 +++-
2 files changed, 52 insertions(+), 2 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index
separate patch.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |6 ++
target-xtensa/helper.c|1 +
target-xtensa/helpers.h |8 ++
target-xtensa/op_helper.c | 172 +
target-xtensa/translate.c | 134
- base + offset load/store operations for 1/2/4 byte values;
- cache operations (not implemented);
- multiprocessor synchronization operations.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |1 +
target-xtensa/translate.c | 88 +
2
- mark privileged opcodes with ring check;
- make debug exception on exception handler entry.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h | 91 +
target-xtensa/helper.c| 39 ++-
target-xtensa/helpers.h |2 +
target-xtensa
- access to Special Registers (wsr, rsr);
- access to User Registers (wur, rur);
- misc. operations option (value clamp, sign extension, min, max);
- conditional moves.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 147 +
1 files
See ISA, 4.3.3 for details.
Enable bit of LITBASE may be stored separately for further speedup.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |1 +
target-xtensa/helper.c|1 +
target-xtensa/translate.c | 18 --
3 files changed, 18 insertions(+), 2
Big endian opcode decoding is slightly different.
Signed-off-by: Max Filippov
---
configure |7 ---
hw/xtensa_sample.c|6 +-
target-xtensa/translate.c | 31 +--
3 files changed, 38 insertions(+), 6 deletions(-)
diff --git a
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 60 -
1 files changed, 59 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index faf1adc..d635229 100644
--- a/target-xtensa/translate.c
;t go to sleep, but just sets PS.INTLEVEL. Timer may be used
to avoid busy looping.
Signed-off-by: Max Filippov
---
hw/xtensa_pic.c | 43
target-xtensa/cpu.h | 33 +++
target-xtensa/helper.c| 79 +++-
t
All operations in this group are no-ops, because cache ought to be
transparent to applications. However cache may be abused, then we'll
need to actually implement these opcodes.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 95 +++
See ISA, 4.7.1.3 for details.
Window check is inserted before commands that push "used register
watermark" beyond its current level. Used register watermark is reset on
instructions that change WINDOW_BASE/WINDOW_START SRs.
Signed-off-by: Max Filippov
---
target-xtensa/translat
looping code verifies actual LEND value.
Invalidation may be avoided for the TB at the new LEND address if
there's a way to associate LEND address with TB at compilation time and
later verify that it doesn't change.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |3 ++
tar
Tensilica iss provides support for applications running in freestanding
environment through SIMCALL command. It is used by Tensilica libc to
access argc/argv, for file I/O, etc.
Signed-off-by: Max Filippov
---
target-xtensa/helpers.h |1 +
target-xtensa/op_helper.c |7 ++
target
See ISA, 4.4.3 for details.
Vector addresses recorded in core configuration are absolute values that
correspond to default VECBASE value.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |2 ++
target-xtensa/helper.c| 18 --
target-xtensa/translate.c |1
See ISA, 4.4.4 for details.
Correct (aligned as per ISA) address for unaligned access is generated
in case this option is not enabled.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 33 +++--
1 files changed, 31 insertions(+), 2 deletions(-)
diff
Signed-off-by: Max Filippov
---
hw/xtensa_sample.c|1 +
target-xtensa/cpu.h |2 ++
target-xtensa/translate.c |7 +++
3 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/hw/xtensa_sample.c b/hw/xtensa_sample.c
index b1da7e1..797a0c4 100644
--- a/hw
> +#elif defined(TARGET_XTENSA)
> + if (interrupt_request & CPU_INTERRUPT_HARD) {
> + env->exception_index = EXC_IRQ;
> + do_interrupt(env);
> + next_tb = 0;
> + }
Looks like I've moved this
>> + HAS_OPTION(XTENSA_OPTION_MISC_OP);
>> + {
>> +#define gen_bit_bisect(w) do { \
>> + int label = gen_new_label(); \
>> + tcg_gen_brcondi_i32(TCG_COND_LTU, tmp, 1 << (w), label); \
>> + tcg_gen_shri_i32(tmp, tmp, (w)); \
>> + tcg_
>> case 2: /*RST2*/
>> - TBD();
>> + if (_OP2 >= 12) {
>> + HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
>> + int label = gen_new_label();
>> + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
>> + gen_exce
>> To track immediate values written to SAR? You mean that there may be
>> some performance difference of fixed size shift vs indirect shift and
>> TCG is able to tell them apart?
>
> Well, not really fixed vs indirect, but if you know that the value
> in the SAR register is in the right range, you
> > This is a case where you almost certainly want to check this
> > condition inside QEMU and translate the opcode differently.
> >
> > See cpu_get_tb_cpu_state, which sets bits in *flags. These
> > flags can then be checked in tb->flags while translating.
> > At which point you'd avoid all the
r 1
Signed-off-by: Max Filippov
---
configure |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/configure b/configure
index 6c77fbb..580cd4d 100755
--- a/configure
+++ b/configure
@@ -2200,7 +2200,7 @@ cat > $TMPC << EOF
int main(void)
{
-int efd = eve
- ITLB/DTLB ways 5 and 6 have 4 and 8 entries respectively;
- ITLB/DTLB way 6 attr field is set to 3 on reset.
Signed-off-by: Max Filippov
---
target-xtensa/helper.c |2 +-
target-xtensa/overlay_tool.h |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target
> I oprofiled QEMU with some workloads, i.e. SPECjbb on Ubuntu Linux, i
> see QEMU spent about 60 - 70% of the time in the code cache ( code
> cache size is 256MB ). but I want to know which TB takes the most
> amount of time.
I doubt that it's possible to profile TB code by external tools without
> > Do you have a static libgthread-2.0? (ie /usr/lib/libgthread-2.0.a or
> > equivalent).
> Nope, this is what I have:
>
> /usr/lib64/libgthread.so
> /usr/lib64/libgthread-2.0.so
> /usr/lib64/libgthread-1.2.so.0
> /usr/lib64/libgthread-1.2.so.0.0.10
>
> *but*, just downloaded the source rpm and
> >>> So, somebody at Fedora doesn't like static (.a) files very much, it
> >>> seems. I could easily correct this, enable static building and have these
> >>> installed, I think.
> >>
> >> There's glib2-static in Fedora:
> >>
> >> $ rpm -ql glib2-static
> >> /usr/lib64/libgio-2.0.a
> >> /usr/lib
> It fails some other way ):
>
> $ make V=1
> gcc -m64 -D_FORTIFY_SOURCE=2 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64
> -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef
> -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing
> -fstack-protector-all -Wendif-labels -Wmissing
> Even though I executed "./configure --target-list="arm-linux-user
> armeb-linux-user" --disable-kvm --disable-strip --disable-xen --disable-spice
> --disable-werror --disable-sdl --disable-vnc --disable-bluez
> --disable-check-utests --disable-smartcard --disable-usb-redir --static" the
> -lu
> > Did configure reported 'usb net redir' as 'no'?
> > Could you try configure and build in a clean directory?
> [mr-4@test1 qemu-1.0-rc3]$ ./configure --target-list="arm-linux-user
> armeb-linux-user" --disable-kvm --disable-strip --disable-xen --disable-spice
> --disable-werror --disable-sdl -
--*dir) option pattern precede --{en,dis}able-usb-redir) patterns in the
option analysis switch, making the latter options have no effect.
Signed-off-by: Max Filippov
---
configure |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configure b/configure
index f033438
> >> /usr/lib/gcc/x86_64-redhat-linux/4.6.1/../../../../lib64/libglib-2.0.a(gmem.o):(.note.stapsdt+0x24):
> >> undefined reference to `glib_mem__alloc_semaphore'
> >> /usr/lib/gcc/x86_64-redhat-linux/4.6.1/../../../../lib64/libglib-2.0.a(gmem.o):(.note.stapsdt+0x7c):
> >> undefined reference to `
Is there any solution to this?
>>> Traditional: it may be fixed in the mainline already, F15 has version
>>> 2.28.8, whereas mainline tip is 2.31.2.
>>> However nothing in the git log suggests that.
>>
>> FWIW Ubuntu Oneiric has glib2 2.30.0 and doesn't seem to have this problem.
> Just compi
>>> In fact, what cases is this supposed to be matching? All
>>> the documented --thingydir options are handled explicitly
>>> earlier in the case statement.
>>>
>>> Paolo, you added this case in commit 6bde81cb0, but the
>>> commit message doesn't give any rationale; what's it for?
>>
>> There wer
overrides
directories for their distribution.
Replace --*dir with exact option names.
Signed-off-by: Max Filippov
---
configure | 24 ++--
1 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/configure b/configure
index f033438..3154307 100755
--- a/configure
+++ b
overrides
directories for their distribution.
Replace --*dir with exact option names.
Signed-off-by: Max Filippov
---
v2 -> v3 changes: add --htmldir
---
configure | 26 --
1 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/configure b/configure
index f033
overrides
directories for their distribution.
Replace --*dir with exact option names.
Signed-off-by: Max Filippov
---
v2 -> v3 changes: add --htmldir
v3 -> v4 changes: collapse cases, include rationale into the configure
---
configure | 10 --
1 files changed, 8 insertions(+), 2 del
>> Also all the registers which are pushed to the stack,
>> "r3, r4, r5, r6, r7, lr" are cleared to zero
>
> That is odd. I wonder if the processor is resetting for some reason.
Another other possibility is stack pointer pointing to a region w/o
underlying physical memory.
--
Thanks.
-- Max
> Breakpoint 7, cpu_arm_exec (env=0x102033200) at ~/qemu-0.15.0/cpu-exec.c:557
> 557 next_tb = tcg_qemu_tb_exec(env, tc_ptr);
> (gdb) p/x env->regs
> $13 = {0x4002c00c, 0x20, 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0,
> 0x0, 0x30, 0x10007fa8, 0x560d, 0x560c}
> (gdb) s
> This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt
> from HPCN Lab KICS UET Lahore.
Shouldn't 'Signed-off-by' lines for mentioned persons be present in
the relevant patches if this is a team work?
--
Thanks.
-- Max
> Misgenerated code might not be an issue now since we have tested our
> framework
> in LLVM-only mode. I think the problem still is about the link/unlink stuff.
> The first problem I have while lowering the threshold is the broken one
> generate
> a few traces (2, actually) that a work one does
>> There's no attachment in this mail. I can try to help you resolving it
>> if you provide more information.
>
> Sorry about that, see the attachment please. What kind of information you
> want
> to know?
If your code is available online I can try it myself, the question is
where is it hosted t
>> >> I found this in HACKING:
>> >>
>> >> Please note that NULL check for the g_malloc result is redundant and
>> >> that g_malloc() call with zero size is not allowed.
>> >
>> > So we have:
>> >
>> > 1. You should not request 0 bytes from g_malloc().
>>
>> I think this was related to qemu_ma
and lines, etc).
> 67882fd177389527510eb36b3f7712011a835545 is the first bad commit
> commit 67882fd177389527510eb36b3f7712011a835545
> Author: Max Filippov
> Date: Tue Sep 6 03:55:28 2011 +0400
>
>target-xtensa: implement narrow instructions
>
>Instructions with op0 >= 8 are 2 bytes lon
e anything that would compile for x86 targets.
>> 67882fd177389527510eb36b3f7712011a835545 is the first bad commit
>> commit 67882fd177389527510eb36b3f7712011a835545
>> Author: Max Filippov
>> Date: Tue Sep 6 03:55:28 2011 +0400
>>
>> target-xtensa: implement narrow instructions
>>
>>
Hi,
this series adds two new xtensa instructions:
- s32nb is a new core instruction;
- depbits is enabled by dedicated option.
Max Filippov (2):
target-xtensa: implement depbits instruction
target-xtensa: implement S32NB
target-xtensa/cpu.h | 1 +
target-xtensa/overlay_tool.h
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