model where chiplet control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Reviewed-by: Cédric Le Goater
Signed-off-by: Chalapathi V
Signed-off-by: Nicholas Piggin
---
hw/ppc/meson.build | 1 +
hw/ppc/pnv_n1_chiplet.c
interface so that
all child buses and devices are automatically reset.
Reviewed-by: Cédric Le Goater
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv_i2c.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv_i2c.c b/hw/ppc
508238 7680722
After 34s 73 1143
Tested-by: BALATON Zoltan
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 43 +++--
1 file changed, 37 insertions(+), 6
-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 35 ++-
1 file changed, 10 insertions(+), 25 deletions(-)
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index f87d35379a..c140f3c96d 100644
--- a/target/ppc/mmu_helper.c
to TBL, TBU, WR_TBL, WR_TBU, respectively.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 8
target/ppc/helper_regs.c | 10 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index
ead TBL on 32-bit.
Change SPR 268 to be called TB on 64-bit implementations.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 4
target/ppc/ppc-qmp-cmds.c | 4
2 files changed, 8 insertions(+)
diff --git a/target/ppc/helper_regs.c b/target/
From: Chalapathi V
This part of the patchset connects the nest1 chiplet model to p10 chip.
Reviewed-by: Cédric Le Goater
Signed-off-by: Chalapathi V
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 15 +++
include/hw/ppc/pnv_chip.h | 2 ++
2 files changed, 17
image, boots it and downloads and installs
the qemu package, then boots a virtual machine under it, re-using the
original Alpine VM image.
Signed-off-by: Nicholas Piggin
---
MAINTAINERS | 1 +
tests/avocado/ppc_hv_tests.py | 202 ++
2 files
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2108
Fixes: 55a7fa34f89 ("target/ppc: Machine check on invalid real address access
on POWER9/10")
Fixes: 5a5d3b23cb2 ("target/ppc: Add SRR1 prefix indication to interrupt
handlers")
Signed-off-by: Nicholas Piggin
---
targ
users should be low.
QEMU should follow the ISA for register name convention (where there is
no established GDB name).
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c| 20 ++--
target/ppc/helper_regs.c | 2 +-
2 files changed, 11 insertions
t@host build]#
Reported-by: Kowshik Jois
Tested-by: Kowshik Jois
Reviewed-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
inde
POWER10 is the latest pseries CPU.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 0028ce0b67..b442d18317 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
Goater
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
MAINTAINERS| 10 +-
hw/misc/pca9554.c | 328 +
include/hw/misc/pca9554.h | 36
include/hw/misc/pca9554_regs.h | 19 ++
4 files changed, 391 insertions
-by: Harsh Prateek Bora
Tested-by: Harsh Prateek Bora
Reviewed-by: Cédric Le Goater
Tested-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/translate/vsx-impl.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc
From: Glenn Miles
Create a new powernv machine type, powernv10-rainier, that
will contain rainier-specific devices.
Reviewed-by: Cédric Le Goater
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 24 ++--
1 file changed, 22 insertions(+), 2
From: Philippe Mathieu-Daudé
Check tcg_enabled() before calling softmmu_resize_hpt_prepare()
and softmmu_resize_hpt_commit() to allow the compiler to elide
their calls. The stubs are then unnecessary, remove them.
Reviewed-by: Nicholas Piggin
Signed-off-by: Philippe Mathieu-Daudé
Signed-off
, because the QEMU ppc timebase
implementation is always synchronised acros all cores.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/meson.build | 1 +
hw/ppc/pnv_chiptod.c | 454 +++
hw/ppc/trace-events | 4
Rather than tlbwe_lo always flushing all TCG TLBs, have it flush just
those corresponding to the old software TLB, and only if it was valid.
Tested-by: BALATON Zoltan
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 10 --
1 file changed, 8
et control registers.
Reviewed-by: Cédric Le Goater
Signed-off-by: Chalapathi V
Signed-off-by: Nicholas Piggin
---
hw/ppc/meson.build | 1 +
hw/ppc/pnv_nest_pervasive.c | 208
include/hw/ppc/pnv_nest_pervasive.h | 32 +
includ
From: Saif Abrar
SPR's CFAR, DEC, HDEC, TB-L/U are not implemented as part of CPUPPCState.
Hence, gdbstub is not able to access them using (CPUPPCState *)env->spr[] array.
Update gdb_get_spr_reg() method to handle these SPR's specifically.
Reviewed-by: Nicholas Piggin
Signed-off-by: Saif Ab
Le Goater
Signed-off-by: Nicholas Piggin
---
tests/avocado/boot_linux_console.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.py
index 3f0180e1f8..af104fff1c 100644
--- a/tests/avocado
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 15
hw/ppc/pnv_chiptod.c | 132 +++
include/hw/ppc/pnv.h | 2 +
include/hw/ppc/pnv_chiptod.h | 4 ++
target/ppc/cpu.h | 13
5 files changed, 166 insertions
lenn Miles
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 78f5c6262a..97bdfb2d1e 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1900,7 +1900,19 @@ static void pnv_rainie
and
copyrights from the original spapr_hcall.c at commit 9fdf0c2995.
Signed-off-by: Philippe Mathieu-Daudé
[npiggin: Update file description.]
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_softmmu.c | 9 +
1 file changed, 9 insertions(+)
Add test for POWER10.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
tests/avocado/boot_linux_console.py | 8
1 file changed, 8 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.py
index af104fff1c..a00202df3c 100644
Flushing the TCG TLB pages that cache a software TLB is a common
operation, factor it into its own function.
Tested-by: BALATON Zoltan
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 24 +---
1 file changed, 13 insertions(+), 11
Wire the ChipTOD model to powernv9 and powernv10 machines.
Suggested-by-by: Cédric Le Goater
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 30 ++
include/hw/ppc/pnv_chip.h | 3 +++
2 files changed, 33 insertions
-by: Cedric Le Goater
Reviewed-by: Cédric Le Goater
Tested-by: Kowshik Jois
Signed-off-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_irq.c | 6 --
include/hw/ppc/spapr_irq.h | 14 +-
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/hw
-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 949ae87f4f..68632bf54e 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -808,13 +808,6
and certain other proprietary firmware.
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/timebase_helper.c | 105 ---
target/ppc/translate.c | 42 +-
2 files changed, 136 insertions(+), 11 deletions(-)
diff --git a/target/ppc
for.
This does not seem to affect any upstream test case that I can see, but
it does cause occasional hangs in the proposed ppc_hv_tests.py test,
usually when run on KVM hosts that are fast enough to output important
lines early enough to be consumed.
Signed-off-by: Nicholas Piggin
---
tests/avocado
,
still in use by old distros.
Reviewed-by: Thomas Huth
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
docs/about/deprecated.rst | 8
hw/ppc/spapr.c| 1 +
roms/skiboot | 2 +-
3 files changed, 10 insertions
Use the default CPU with the pseries machine unless there is a
specific requirement.
Signed-off-by: Nicholas Piggin
---
tests/avocado/migration.py | 1 -
1 file changed, 1 deletion(-)
diff --git a/tests/avocado/migration.py b/tests/avocado/migration.py
index 09b62f813e..be6234b3c2 100644
Reviewed-by: Cédric Le Goater
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
hw/misc/Kconfig | 4
hw/misc/meson.build | 1 +
hw/ppc/Kconfig | 1 +
hw/ppc/pnv.c| 6 ++
4 files changed, 12 insertions(+)
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index
Signed-off-by: Nicholas Piggin
---
hw/misc/pca9552.c | 50 +--
include/hw/misc/pca9552.h | 3 ++-
2 files changed, 45 insertions(+), 8 deletions(-)
diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c
index f00a149d61..2ae13af35e 100644
--- a/hw/misc
hypervisor interface, called vhyp.
Reviewed-by: Nicholas Piggin
Signed-off-by: Philippe Mathieu-Daudé
[npiggin: Pick a different name, explain it in changelog.]
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_hcall.c | 4 ++--
hw/ppc/spapr_softmmu.c | 4
From: Philippe Mathieu-Daudé
To reduce the use of the term 'softmmu', rename spapr_softmmu.c
to spapr_vhyp_mmu.c.
Reviewed-by: Nicholas Piggin
Signed-off-by: Philippe Mathieu-Daudé
[np: change name]
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw/ppc/meson.build
cc99318 ("docs/devel: rationalise unstable gitlab tests under
FLAKY_TESTS") changed this to being flaky but it isn't really, it just
had a long runtime.
So take the SPEED=slow variable from qtests and introduce it to avocado,
and make these tests require it.
Reviewed-by: Cédric Le Goater
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
hw/ppc/Kconfig | 1 +
hw/ppc/pnv.c | 25 +
include/hw/ppc/pnv.h | 1 +
3 files changed, 27 insertions(+)
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 99d571fa20..0e5acfd1c4 100644
--- a/hw
Have 440 tlbwe flush only the range corresponding to the addresses
covered by the software TLB entry being modified rather than the
entire TLB. This matches what 4xx does.
Tested-by: BALATON Zoltan
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 2 +-
1
POWER CPUs support hash and radix MMU modes. Linux supports running in
either mode, but defaults to radix. To keep up testing of QEMU's hash
MMU implementation, add some Linux hash boot tests.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
tests/avocado/ppc_powernv.py | 23
POWER10 is the latest IBM Power machine. Although it is not offered in
"OPAL mode" (i.e., powernv configuration), so there is a case that it
should remain at powernv9, most of the development work is going into
powernv10 at the moment.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicho
scenario. Existing code was doing the opposite
and setting INPUT0/1 bit to a 1 when the LSn bit was
set to 0, so this commit fixes that.
Reviewed-by: Andrew Jeffery
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
hw/misc/pca9552.c | 18 +-
tests/qtest
ppc has no avocado tests for the KVM backend. Add a KVM boot_linux.py
test for pseries.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
tests/avocado/boot_linux.py | 9 +
1 file changed, 9 insertions(+)
diff --git a/tests/avocado/boot_linux.py b/tests/avocado
- Connected GPIO pin tests of P10 PCA9552 device. Tests
output of pins 0-4 affect input of pins 5-9 respectively.
- PCA9554 GPIO pins test. Tests input and ouput functionality.
Reviewed-by: Cédric Le Goater
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv_i2c.c
-by: Nicholas Piggin
---
target/ppc/cpu.h | 36 ++
target/ppc/timebase_helper.c | 210 ++-
2 files changed, 243 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 0e932838aa..ec14574d14 100644
--- a/target/ppc/cpu.h
The move-to timebase registers TBU and TBL can not be read, and they
can not be written in supervisor mode on hypervisor-capable CPUs.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 31 +++
1 file changed, 23 insertions
On Wed Apr 10, 2024 at 9:55 AM AEST, BALATON Zoltan wrote:
> Real 460EX SoC apparently does not expose a bridge device and having
> it appear on PCI bus confuses an AmigaOS file system driver that uses
> this to detect which machine it is running on. Since values written
> here by firmware are
On Tue Apr 16, 2024 at 7:43 PM AEST, BALATON Zoltan wrote:
> On Tue, 16 Apr 2024, Nicholas Piggin wrote:
> > On Wed Apr 10, 2024 at 9:03 PM AEST, BALATON Zoltan wrote:
> >> On Wed, 10 Apr 2024, Nicholas Piggin wrote:
> >>> On Wed Apr 10, 2024 at 9:55 AM AEST, BAL
the XSCOM bridge
implementation, and pnv_adu.c implements the ADU registers and other
functions.
So far, just the ADU no-op registers in the pnv_xscom.c default handler
are moved over to the adu model.
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv_adu.h | 34
include/hw/ppc
.
This requires a linkage between adu and lpc, which allows adu to
perform memory access in the lpc space.
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv_adu.h | 7
include/hw/ppc/pnv_lpc.h | 5 +++
hw/ppc/pnv.c | 4 ++
hw/ppc/pnv_adu.c | 91
address space.
Patch 2 implements one of the memory access functions of the ADU that
drives access to LPC address space from XSCOM register operations which
is non-trivial but there are similar examples already in tree.
Thanks,
Nick
Nicholas Piggin (2):
ppc/pnv: Begin a more complete ADU LPC model
On Wed Apr 10, 2024 at 9:03 PM AEST, BALATON Zoltan wrote:
> On Wed, 10 Apr 2024, Nicholas Piggin wrote:
> > On Wed Apr 10, 2024 at 9:55 AM AEST, BALATON Zoltan wrote:
> >> Real 460EX SoC apparently does not expose a bridge device and having
> >> it appear on PCI b
ret = -1;
> -raddr = (hwaddr)-1ULL;
> +*prot = 0;
This is still doing some sneaky used-uninit things which I would
rather not without a comment, but okay we can try untangle things
more after this series.
Reviewed-by: Nicholas Piggin
> pr = FIELD_EX6
On Thu May 9, 2024 at 9:36 AM AEST, BALATON Zoltan wrote:
> mmubooke_get_physical_address() only uses the raddr and prot fields
> from mmu_ctx_t. Pass these directly instead of using a ctx struct.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> targe
On Thu May 9, 2024 at 9:36 AM AEST, BALATON Zoltan wrote:
> Add a new mmu-booke.c file for BookE and related MMU bits from
> mmu_common.c.
>
Nice work.
Acked-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/cpu.h| 4 -
> target/p
On Thu May 9, 2024 at 9:36 AM AEST, BALATON Zoltan wrote:
> Merge the code fetch and data access cases in a common switch.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 52 -
>
On Thu May 9, 2024 at 1:17 AM AEST, BALATON Zoltan wrote:
> On Wed, 8 May 2024, Nicholas Piggin wrote:
> > On Wed May 8, 2024 at 10:14 AM AEST, BALATON Zoltan wrote:
> >> Most exceptions are raised with nip pointing to the faulting
> >> instruction but the sc instr
On Thu May 9, 2024 at 1:23 AM AEST, BALATON Zoltan wrote:
> On Wed, 8 May 2024, Nicholas Piggin wrote:
> > On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> >> Checking if a page protection bit is set for a given access type is a
> >> common operation. Add
On Thu May 9, 2024 at 1:25 AM AEST, BALATON Zoltan wrote:
> On Wed, 8 May 2024, Nicholas Piggin wrote:
> > On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> >> Move setting error_code that appears in every case out in front and
> >> hoist the common fal
> called in ppc_cpu_reset_hold() so likely we never get here but to make
> sure add a case to ppc_xlate() to the same effect.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 12 ++--
> 1 file changed, 2 insertions(+), 10 deleti
On Thu May 9, 2024 at 9:36 AM AEST, BALATON Zoltan wrote:
> Move the debug logging within ppc6xx_tlb_check() from after its only
> call to simplify the caller.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc
in this file.
get_physical_address_wtlb and mmu_ctx_t is becoming basically 6xx
specific after this. Nice.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/internal.h | 17 +
> target/ppc/mmu_common.c | 17 ++---
> 2 files
On Thu May 9, 2024 at 9:36 AM AEST, BALATON Zoltan wrote:
> Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
> reduce ppc_jumbo_xlate() further.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/
On Thu May 9, 2024 at 9:35 AM AEST, BALATON Zoltan wrote:
> On Wed, 8 May 2024, Nicholas Piggin wrote:
> > On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> >> Checking if a page protection bit is set for a given access type is a
> >> common operation. Add
On Thu May 9, 2024 at 9:33 AM AEST, BALATON Zoltan wrote:
> On Wed, 8 May 2024, Nicholas Piggin wrote:
> > On Tue May 7, 2024 at 10:31 PM AEST, BALATON Zoltan wrote:
> >> On Tue, 7 May 2024, Nicholas Piggin wrote:
> >>> What do you think about adding mmu-book
On Thu May 9, 2024 at 9:36 AM AEST, BALATON Zoltan wrote:
> mmubooke206_get_physical_address() only uses the raddr and prot fields
> from mmu_ctx_t. Pass these directly instead of using a ctx struct.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> --
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/spapr.h | 1 +
hw/ppc/spapr.c | 1 +
hw/ppc/spapr_caps.c| 1 +
3 files changed, 3 insertions(+)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 4aaf23d28f..f6de3e9972 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/p
On Fri May 3, 2024 at 3:44 PM AEST, Cédric Le Goater wrote:
> On 5/3/24 06:51, Nicholas Piggin wrote:
> > On Thu May 2, 2024 at 6:47 PM AEST, Cédric Le Goater wrote:
> >> On 5/1/24 14:39, Nicholas Piggin wrote:
> >>> On Wed Apr 17, 2024 at 9:25 PM AEST, Cédric Le G
ent hardware and focus on newer CPUs and platforms.
>
> Signed-off-by: Cédric Le Goater
Acked-by: Nicholas Piggin
> ---
> v2: fixed header line
>
> docs/about/deprecated.rst | 8
> hw/ppc/ppc405_boards.c| 1 +
> 2 files changed, 9 insertions(+)
>
>
On Tue May 7, 2024 at 10:31 PM AEST, BALATON Zoltan wrote:
> On Tue, 7 May 2024, Nicholas Piggin wrote:
> > What do you think about adding mmu-book3e.c instead?
>
> I have considered that but found that some functions have to be in the
> same file and declared static for the
On Wed May 8, 2024 at 2:02 AM AEST, BALATON Zoltan wrote:
> On Tue, 7 May 2024, Nicholas Piggin wrote:
> > On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> >> This flag for split instruction/data TLBs is only set for 6xx soft TLB
> >> MMU model and not used o
r so no need to keep these separate functions and
> combining them simplifies the caller allowing further restructuring.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 26 --
> 1 file changed, 12 insertion
return -3;
> +}
Function is already inconsistent with assigning ret and falling
through to the return ret at the end vs returning immediately, so
okay since you're tidying it up.
Reviewed-by: Nicholas Piggin
> +/* Page address translation */
> +
On Tue Apr 23, 2024 at 4:30 PM AEST, Harsh Prateek Bora wrote:
> + qemu-devel
>
> On 4/23/24 11:40, Harsh Prateek Bora wrote:
> > On ppc64, the PowerVM hypervisor runs with limited memory and a VCPU
> > creation during hotplug may fail during kvm_ioctl for KVM_CREATE_VCPU,
> > leading to
On Wed Apr 24, 2024 at 8:31 AM AEST, BALATON Zoltan wrote:
> This series does some further clean up mostly around BookE MMU to
> untangle it from other MMU models. It also contains some other changes
> that I've come up with while working on this. The first 3 patches are
> from the last exception
On Thu May 2, 2024 at 6:32 PM AEST, Cédric Le Goater wrote:
> Hello Nick,
>
>
> >>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> >>> index 5869aac89a..eb9dbc62dd 100644
> >>> --- a/hw/ppc/pnv.c
> >>> +++ b/hw/ppc/pnv.c
> >>> @@ -1642,6 +1642,8 @@ static void pnv_chip_power9_realize(DeviceState
>
On Wed Apr 24, 2024 at 7:30 PM AEST, Cédric Le Goater wrote:
> This helper routine uses the machine definition, sockets, cores and
> threads, to loop on all CPUs of the machine. Replace CPU_FOREACH()
> with it.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Nicholas Piggin
On Thu May 2, 2024 at 6:47 PM AEST, Cédric Le Goater wrote:
> On 5/1/24 14:39, Nicholas Piggin wrote:
> > On Wed Apr 17, 2024 at 9:25 PM AEST, Cédric Le Goater wrote:
> >> Hello Nick,
> >>
> >> On 4/17/24 13:02, Nicholas Piggin wrote:
> >>> T
On Sat Apr 27, 2024 at 12:32 AM AEST, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
> > with Power11 being the newest supported Power processor in QEMU.
>
> This is too early. We should merge Power11
On Wed Apr 17, 2024 at 9:25 PM AEST, Cédric Le Goater wrote:
> Hello Nick,
>
> On 4/17/24 13:02, Nicholas Piggin wrote:
> > This implements a framework for an ADU unit model.
> >
> > The ADU unit actually implements XSCOM, which is the bridge between MMIO
> >
On Wed Apr 17, 2024 at 10:25 PM AEST, Cédric Le Goater wrote:
> On 4/17/24 13:02, Nicholas Piggin wrote:
> > One of the functions of the ADU is indirect memory access engines that
> > send and receive data via ADU registers.
> >
> > This implements the ADU LPC
instruction exceptions
when using new POWER10 sync variants that add new fields, after this
the instructions are accepted and are implemented as supersets of
the new behaviour, as intended.
Signed-off-by: Nicholas Piggin
---
target/ppc/insn32.decode | 7 ++
target/ppc/translate.c
POWER10 adds a new field to sync for store-store syncs, and some
new variants of the existing syncs that include persistent memory.
Implement the store-store syncs and plwsync/phwsync.
Signed-off-by: Nicholas Piggin
---
target/ppc/insn32.decode | 6 ++--
target/ppc/translate/misc
probably add at least patch 1 to -stable, so the Linux changes
can be upstreamed a bit sooner.
Thanks,
Nick
Nicholas Piggin (3):
target/ppc: Move sync instructions to decodetree
target/ppc: Fix embedded memory barriers
target/ppc: Add ISA v3.1 variants of sync instruction
target/ppc
Memory barriers are supposed to do something on BookE systems, these
were probably just missed during MTTCG enablement, maybe no targets
support SMP. Either way, add proper BookE implementations.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate/misc-impl.c.inc | 4 ++--
1 file changed, 2
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> The helper_rac function is defined but not used, remove it.
>
> Fixes: 005b69fdcc (target/ppc: Remove PowerPC 601 CPUs)
> Signed-off-by: BALATON Zoltan
Reviwed-by: Nicholas Piggin
> ---
> target/ppc/helper.h |
er and avoid computing it when not needed.
>
> Signed-off-by: BALATON Zoltan
Reviwed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
>
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> The real mode handling is identical in the remaining switch cases.
> Split off these common real mode cases into a separate conditional to
> leave only the else branches in the switch that are different.
>
Reviewed-by: Nic
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Fix several qemu_log_mask() calls that are misindented.
Acked-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 42 -
> 1 file chan
nt i, j, ways, ret = -1;
>
> for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
> -int ways = booke206_tlb_ways(env, i);
Don't need to bring the ways variable into a larger scope I think?
Otherwise,
Reviewed-by: Nicholas Piggin
> -
> +ways = booke206_tlb_ways(env, i);
>
so using MMU_DATA_LOAD here seems wrong so replace it with
> access_type here as well that yields the same result. This also makes
> these calls the same as the data access branch further down.
Looks right.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
>
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This type is only used within mmu_common.c. Move its definition from
> internal.h to there.
This can be squashed with the previous patch unexport the
remaining user.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BA
er and avoid computing it when not needed.
>
> Signed-off-by: BALATON Zoltan
Reviwed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 25 -
> 1 file changed, 12 insertions(+), 13 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/pp
.
Hopefully the compiler should be able to work it out, but IMO it
reads better with your change.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> The default case will catch this and abort the same way and there is
> still a warning about it in ppc_tlb_invalidate_all() so drop these
> from mmu_common.c to simplify this code.
Reviewed-by: Nicholas Piggin
>
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Rename to ppc6xx_tlb_get_bat() to match other similar names in the
> same file.
>
> Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 6 +++---
> 1 file changed, 3 inser
y */
if (env->nb_BATs != 0) {
int ret = get_bat_6xx_tlb(env, ctx, eaddr, access_type);
if (ret >= 0) {
return ret;
}
}
Otherwise,
Reviewed-by: Nicholas Piggin
> +/* Perform segment based translation when no BATs matched */
> pr =
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> BookE does not have real mode so split off and handle it first in
> get_physical_address_wtlb() before checking for real mode for other
> MMU models.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
>
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 25 +
> 1 file changed, 9 insertions(+), 16 deletions(-)
>
> diff --git a/target/ppc/mmu_com
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