Hi, Mark,
-Original Message-
From: Yang, Wenyou
Sent: 2013年4月2日 13:50
To: 'Mark Brown'
Cc: linux-arm-ker...@lists.infradead.org; grant.lik...@secretlab.ca;
richard.gen...@gmail.com; plagn...@jcrosoft.com; Ferre, Nicolas; Lin, JM;
spi-devel-general@lists.sourceforge.net;
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On Mon, Apr 1, 2013 at 9:22 PM, Marek Vasut ma...@denx.de wrote:
On Mon, Apr 1, 2013 at 4:11 PM, Marek Vasut ma...@denx.de wrote:
+#define TXRX_WRITE 1 /* This is a write */
+#define TXRX_DEASSERT_CS 2 /* De-assert CS at end of txrx */
btw. is it necessary to
On Mon, Apr 1, 2013 at 7:36 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 04/01/2013 01:52 PM, Trent Piepho wrote:
On Tue, Mar 26, 2013 at 7:37 PM, Stephen Warren swar...@wwwdotorg.org
wrote:
Allow SPI masters to define the set of bits_per_word values they support.
If they do this, then
On 3/20/2013 4:44 PM, Sekhar Nori wrote:
Grant,
On 3/20/2013 4:16 PM, Manjunathappa, Prakash wrote:
Patch enables support for m25p64 SPI flash support on
da850-EVM.
With your ack, I would like to merge this series through davinci tree
for v3.10. This will help manage dependencies for DT
On Tue, Apr 2, 2013 at 2:45 AM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
I think if we're getting down to looking at the disassembly we're
perhaps overoptimising - in the common case we're then going to start
the hardware doing a data transfer which will take rather more time than
Dear Trent Piepho,
On Mon, Apr 1, 2013 at 9:22 PM, Marek Vasut ma...@denx.de wrote:
On Mon, Apr 1, 2013 at 4:11 PM, Marek Vasut ma...@denx.de wrote:
+#define TXRX_WRITE 1 /* This is a write */
+#define TXRX_DEASSERT_CS 2 /* De-assert CS at end of txrx
*/
On 2 April 2013 12:12, Trent Piepho tpie...@gmail.com wrote:
On Tue, Apr 2, 2013 at 2:45 AM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
I think if we're getting down to looking at the disassembly we're
perhaps overoptimising - in the common case we're then going to start
the
In DMA mode the chip select control bits would be ORed into the CTRL0
register without first clearing the bits. This means that after
addressing slave 1 the bit would be still be set when addressing slave
0, resulting in slave 1 continuing to be addressed.
The message handing function would pass
The ssp struct has a clock rate field, to provide the actual value, in Hz,
of the SSP output clock (the rate of SSP_SCK) after mxs_ssp_set_clk_rate()
is called. It should be read-only, except for mxs_ssp_set_clk_rate().
For some reason the spi-mxs driver decides to write to this field on init,
There are two bits which control the CS line in the CTRL0 register:
LOCK_CS and IGNORE_CRC. The latter would be better named DEASSERT_CS
in SPI mode.
LOCK_CS keeps CS asserted though the entire transfer. This should
always be set. The DMA code will always set it, explicitly on the
first
These functions do nothing but one single writel call and are only
called in once. And the names really aren't accurate or clear, since
they don't enable or disble SPI. Rather they set the bit that
controls the state of CS at the end of transfer. It easier to follow
the code to just set this
There are three flag arguments to the PIO and DMA txrx functions. Two
are passed as pointers to integers, even though they are input only
and not modified, which makes no sense to do. The third is passed as
an integer.
The compiler must use an argument register or stack variable for each
flag
mxs_spi_setup_transfer() would set the SSP SCK rate every time it was
called, which is before each transfer. It is uncommon for the SCK rate to
change between transfers and this causes unnecessary reprogramming of the
clock registers. Changed to only set the rate when it has changed.
This
It's consistent with all the other spi drivers that way.
Signed-off-by: Trent Piepho tpie...@gmail.com
Cc: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Shawn Guo shawn@linaro.org
---
drivers/spi/spi-mxs.c | 10 +-
1 file changed, 5 insertions(+), 5
Because the driver sets the SPI_MASTER_HALF_DUPLEX flag, the spi core
will check transfers to insure they are not full duplex. It's not
necessary to check that in the mxs driver as well.
Signed-off-by: Trent Piepho tpie...@gmail.com
Cc: Marek Vasut ma...@denx.de
Cc: Fabio Estevam
It can't be called with a NULL transfer anymore so it can be
simplified to not check for that.
Change printouts to more closely match what the spi core would print.
I.e., don't print function names. Try to make them clearer.
Fix indention of line-wrapped code to Linux standard.
The transfer
Despite many warnings in the SPI documentation and code, the spi-mxs
driver sets shared chip registers in the -setup method. This method can
be called when transfers are in progress on other slaves controlled by the
master. Setting registers or any other shared state will corrupt those
The spi core already checks for a slave setting mode bits that we
didn't list as supported when the master was registered. There is no
need to do it again in the master driver.
Signed-off-by: Trent Piepho tpie...@gmail.com
Cc: Marek Vasut ma...@denx.de
Cc: Fabio Estevam
On Tue, Apr 2, 2013 at 3:32 AM, Marek Vasut ma...@denx.de wrote:
Don't see anything in CodingStyle that one should be preferred over
the other.
There ain't any I'm aware of, but to paraphrase you, let's keep the format
that's already used in the driver ;-) :
114 if (dev-mode
(http://obfm40.com/usle4mjlh0kqwqguhy/index0.html)
(http://obfm40.com/eql3omzvhw4gegou3l/index1.html)
Félicitations ,
Nous sommes heureux de vous inviter
à gagner votre camping car ou
un chèque de 30 000 euros en participant à notre jeu.
(http://obfm40.com/kllurmlmhisq0cqzis/index2.html)
FROM: Worldwide Registry for Business Professionals
TO: spi-devel-general@lists.sourceforge.net
RE: Worldwide Registry Publication
Hello,
You were recently chosen to represent your professional
community, deeming you eligible for the inclusion in
the new 2013 Edition of Worldwide Registry for
Dear Trent Piepho,
There are two bits which control the CS line in the CTRL0 register:
LOCK_CS and IGNORE_CRC. The latter would be better named DEASSERT_CS
in SPI mode.
LOCK_CS keeps CS asserted though the entire transfer. This should
always be set. The DMA code will always set it,
Dear Trent Piepho,
There are three flag arguments to the PIO and DMA txrx functions. Two
are passed as pointers to integers, even though they are input only
and not modified, which makes no sense to do. The third is passed as
an integer.
The compiler must use an argument register or
Dear Trent Piepho,
In DMA mode the chip select control bits would be ORed into the CTRL0
register without first clearing the bits. This means that after
addressing slave 1 the bit would be still be set when addressing slave
0, resulting in slave 1 continuing to be addressed.
The message
Dear Trent Piepho,
Despite many warnings in the SPI documentation and code, the spi-mxs
driver sets shared chip registers in the -setup method. This method can
be called when transfers are in progress on other slaves controlled by the
master. Setting registers or any other shared state will
Dear Trent Piepho,
It can't be called with a NULL transfer anymore so it can be
simplified to not check for that.
Change printouts to more closely match what the spi core would print.
I.e., don't print function names. Try to make them clearer.
Fix indention of line-wrapped code to Linux
Dear Trent Piepho,
mxs_spi_setup_transfer() would set the SSP SCK rate every time it was
called, which is before each transfer. It is uncommon for the SCK rate to
change between transfers and this causes unnecessary reprogramming of the
clock registers. Changed to only set the rate when it
Dear Trent Piepho,
On Tue, Apr 2, 2013 at 3:32 AM, Marek Vasut ma...@denx.de wrote:
Don't see anything in CodingStyle that one should be preferred over
the other.
There ain't any I'm aware of, but to paraphrase you, let's keep the
format that's already used in the driver ;-) :
On Tue, Apr 02, 2013 at 05:19:44AM -0700, Trent Piepho wrote:
There are two bits which control the CS line in the CTRL0 register:
LOCK_CS and IGNORE_CRC. The latter would be better named DEASSERT_CS
in SPI mode.
LOCK_CS keeps CS asserted though the entire transfer. This should
always be
On Tue, Apr 2, 2013 at 4:31 PM, Marek Vasut ma...@denx.de wrote:
static int mxs_spi_setup(struct spi_device *dev)
{
- int err = 0;
-
if (!dev-bits_per_word)
dev-bits_per_word = 8;
if (dev-mode ~(SPI_CPOL | SPI_CPHA))
return -EINVAL;
-
Dear Trent Piepho,
On Tue, Apr 2, 2013 at 4:31 PM, Marek Vasut ma...@denx.de wrote:
static int mxs_spi_setup(struct spi_device *dev)
{
- int err = 0;
-
if (!dev-bits_per_word)
dev-bits_per_word = 8;
if (dev-mode ~(SPI_CPOL |
Hi, Mark,
-Original Message-
From: Mark Brown [mailto:broo...@opensource.wolfsonmicro.com]
Sent: 2013年4月1日 21:46
To: Yang, Wenyou
Cc: linux-arm-ker...@lists.infradead.org; grant.lik...@secretlab.ca;
richard.gen...@gmail.com; plagn...@jcrosoft.com; Ferre, Nicolas; Lin, JM;
(http://obfm40.com/2hnmcimipydycin5xq/index0.html)
(http://obfm40.com/tunzeilqpu0sqh45co/index1.html)
(http://obfm40.com/03nptiz0p5eyrrwafg/index2.html)
(http://obfm40.com/benw3ijwpxwsimza1j/index3.html)
(http://obfm40.com/u3mvtcg23bky1nwmmo/index4.html)
Hi Mark,
The work is based on Nicolas and Richard's work.
It is based on v3.9-rc5
+ Joachim Eastwood's spi/atmel: fix speed_hz check in
atmel_spi_transfer()
+ the following four patches of the version 7 series, which you've
applied.
- detect the capabilities
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