Re: [PATCH v6 2/4] clk: pistachio: Fix override of clk-pll settings from boot loader

On 08/26, Govindraj Raja wrote: From: Zdenko Pulitika zdenko.pulit...@imgtec.com PLL enable callbacks are overriding PLL mode (int/frac) and Noise reduction (on/off) settings set by the boot loader which results in the incorrect clock rate. PLL mode and noise reduction are defined by the

[PATCH v6 2/4] clk: pistachio: Fix override of clk-pll settings from boot loader

From: Zdenko Pulitika zdenko.pulit...@imgtec.com PLL enable callbacks are overriding PLL mode (int/frac) and Noise reduction (on/off) settings set by the boot loader which results in the incorrect clock rate. PLL mode and noise reduction are defined by the DSMPD and DACPD bits of the PLL control