On 08/26, Govindraj Raja wrote:
> From: Zdenko Pulitika <zdenko.pulit...@imgtec.com>
>
> PLL enable callbacks are overriding PLL mode (int/frac) and
> Noise reduction (on/off) settings set by the boot loader which
> results in the incorrect clock rate.
>
> PLL mode and noise reduction are defined by the DSMPD and DACPD bits
> of the PLL control register. PLL .enable() callbacks enable PLL
> by deasserting all power-down bits of the PLL control register,
> including DSMPD and DACPD bits, which is not necessary since
> these bits don't actually enable/disable PLL.
>
> This commit fixes the problem by removing DSMPD and DACPD bits
> from the "PLL enable" mask.
>
> Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
> Cc: <stable@vger.kernel.org> # 4.1
> Reviewed-by: Andrew Bresitcker <abres...@chromium.org>
> Signed-off-by: Zdenko Pulitika <zdenko.pulit...@imgtec.com>
> Signed-off-by: Govindraj Raja <govindraj.r...@imgtec.com>
> ---
Applied to clk-next
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