Hello,
El 21/06/2011 02:19, Luis Cupido escribió:
Imagine an FPGA and a square wave coming out.
Just that. Nothing more.
(That is what I had in mind when querying about the MSB usage in
the first place.)
My first approach was the ACC MSB
(and that is working already on the bench.)
I
But I forgot to add that the resultant jitter will be also the sampling
rate period (10ns at 100MHz), so I think that the output will not be too
clean... so I'm afraid it will not be a great improvement over using
only the MSB :)
Regards,
Javier
El 21/06/2011 08:37, Javier Herrero escribió:
John,
as usual I second your opinion and I did have already on my mind to suggest
XILINX's DDS compiler to the group too.
However your statement
to provide SFDR up to 150 dB (and I'd notice it if I were
getting much less than that in practice.)
has pushed me up! When I tell the compiler to
Luis,
the information that you are concerned about close carrier spurs that will
pass through the PLL's low pass filter is not precise enough: are you
talking about a few Hz, a few ten Hz, a few 100 Hz away from the carrier or
are you going to build a device for precise timing applications where
In the old days, HI, we used to use 6 dB/bit for SFDR for the DAC as a rule
of thumb. In practice, it needed to be somewhat better. So, even with 6
dB/bit it would require a minimum of 25 bits. Good thing back then, in the
early 70's I was working on ASW stuff at acoustic frequencies and some of
to provide SFDR up to 150 dB (and I'd notice it if I were
getting much less than that in practice.)
has pushed me up! When I tell the compiler to generate me a 150 dB SFDR
DDS
then it produces an block with 28 (!) bits output witdh for the DAC. So, I
am asking myself what wonder-chips
Hi,
I'm an Altera user and would say the DDS core generator
is really very good, I would expect it to be not too different from
Xilinx these days. (does anyone that lives on both worlds know better ?)
lc
ct1dmk.
On 6/21/2011 10:03 AM, Ulrich Bangert wrote:
John,
as usual I second your
Hi Ulrich,
Loop bandwidth could be in the KHz region
or even less.
I could choose more or less freely from Hz to many KHz
but there are obvious tradeoffs and it is hard to decide.
The phase noise of the VCO when I go too narrow versus
the ammount of spurs when I go too wide.
Application is the
Yes that right. Is clear that I would have a 10ns jitter,
So the catch would be to find a scheme to spread spurs out or to push
them away from carrier. Then they would not bother me (would not pass
the PLL).
lc
ct1dmk.
On 6/21/2011 7:43 AM, Javier Herrero wrote:
But I forgot to add that
I've played with the core from altera for a while, but since I was only
interested in 1 bit I'm now playing with my own code. Trivial variations
on the plain old clocked accumulator architecture.
lc
On 6/21/2011 7:37 AM, Javier Herrero wrote:
What it the topology you're using now? Also, I
Hi,
I live in both worlds (more or less :) ), and the tools seems somewhat
similar (I suspect that when one of them includes a feature, the other
tries to catch the rythm and viceversa). I've had a look to the Xilinx
DDS compiler, and it is somewhat different. You can download the free
Clever! At least for your spectral measurements the signal never leaves the
digital domain. What is the width of the multipliers involved in the mixing?
Can you give me a clue, which ADCs you are working with in the front end?
In this application, DDS artifacts would ultimately show up as
On 06/21/11 12:59 AM, Alan Melia wrote:
David Another important factor when considering power supply caps is ripple
current rating. It is generally the ripple current that makes them get warm.
Yes. I must admit I did not give that any thought, which was rather stupid of
me. But I did not buy
Dr. David Kirkby wrote:
I think the usual thumbnail calculation still work for caps if you can
reduce the temperature by 20 degrees they will last at least 4 times as
long. That is an activation energy (Arrhenius eqn) of about 1ev. I also
believe though I cant quote that they are best run at
There is an excellent article about cordic on
http://www.andraka.com/files/crdcsrvy.pdf
There are a lot of other good publications on Ray Andraka's
web site.
I have published a accurate sine/cosine function on www.opencores.org
underhttp://opencores.org/project,sincos
It is VHDL
On 6/21/11 6:14 AM, dk...@arcor.de wrote:
There is an excellent article about cordic on
http://www.andraka.com/files/crdcsrvy.pdf
Yes..good explanation..
So, in the general case where you might want to rotate by an arbitrary
angle at each time step, where the angle doesn't happen
Ohh..
It just came to me..
You're not using CORDIC as a replacement for both the phase accumulator
and cos LUT, but JUST instead of the LUT, so you ARE doing the give me
cos(theta) on every sample.
So then, it's a trade between a big ROM LUT or a bunch o'gates for
CORDIC. And for big N the
So then, it's a trade between a big ROM LUT or a bunch o'gates for
CORDIC. And for big N the bunch o'gates is probably going to be easier:
16 bit phase and wanting 16 bits out would be a 64kbit ROM (assuming you
didn't do the usual thing of only needing 1/4 cycle)..
There is also the
16 bits in is 64K *entries* of 16 bits each, a total of 1 megabit of
ROM. The usual 90/180 degree folding could reduce that to 256 kbit.
Dave
On Tue, Jun 21, 2011 at 7:49 AM, Jim Lux jim...@earthlink.net wrote:
So then, it's a trade between a big ROM LUT or a bunch o'gates for CORDIC.
With all the discussion lately regarding DDS and CORDIC, I'm reminded of a
question that came up some time ago for which I've never found an answer.
Perhaps you enlightened people can enlighten me.
Given a complete DDS chip with a single output channel (e.g. AD9834, AD9835),
why would one
On 6/21/11 9:38 AM, David Martindale wrote:
16 bits in is 64K *entries* of 16 bits each, a total of 1 megabit of
ROM. The usual 90/180 degree folding could reduce that to 256 kbit.
Dave
On Tue, Jun 21, 2011 at 7:49 AM, Jim Luxjim...@earthlink.net wrote:
So then, it's a trade between a
On Tue, Jun 21, 2011 at 10:44 AM, KD0GLS kd0...@mninter.net wrote:
Given a complete DDS chip with a single output channel (e.g. AD9834, AD9835),
why would one device favor a cosine LUT versus a sine LUT?
Are the LUTs really different? Ages ago when I made something like
this I used only 90
On Jun 21, 2011, at 13:39, Chris Albertson wrote:
I used only 90 degrees of the table.
Yes, as did I and most implementations, but why a cosine quarter-table instead
of the more common sine? A quick look at the data sheets (and the waveforms in
the theory-of-op sections) for the two
The cordic needs to compute both sin and cos. You are right that you just need
one or the other if you have one DAC.
-Original Message-
From: Chris Albertson albertson.ch...@gmail.com
Sender: time-nuts-boun...@febo.com
Date: Tue, 21 Jun 2011 11:38:30
To: Discussion of precise time and
Hi Brent,
A quarter table cos is exactly the same as a quarter table sin.
Only backwards, and not telling which quarter it is makes it a
quarter of either sin or cos. For one single output becomes irrelevant
as you only need one.
So I think it is just a matter of taste the name to call it.
Luis
On 06/21/2011 09:03 PM, KD0GLS wrote:
On Jun 21, 2011, at 13:39, Chris Albertson wrote:
I used only 90 degrees of the table.
Yes, as did I and most implementations, but why a cosine quarter-table instead
of the more common sine? A quick look at the data sheets (and the waveforms in
the
Brent,
For the specific case of generating a synchronous FSK signal with a fairly wide
shift there may be a reason. Such an application presumes a high enough ratio
between clock and output frequencies such that the DDS accumulator landing
adequately near zero is a certainty. If the FSK
In message 4e008a73.50...@erols.com, Chuck Harris writes:
and yet, I find that some electrolytic
capacitors that have been run at lower than normal voltage improve markedly
when reformed by applying rated voltage through a 10K resistor for a
couple of hours.
I noticed in a datasheet at one
Light Squared backing off?
http://spectrum.ieee.org/riskfactor/telecom/wireless/lightsquared-tacks-hard-in-the-face-of-opposition-says-it-has-solutions-to-gps-interference
___
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To unsubscribe, go to
There appears to be a lot of news coverage about this.
There was this article in the Register earlier today.
http://www.theregister.co.uk/2011/06/21/lightsquared_gps/
All sorts of interesting information. The suggestion is that
LiughtSquared will move to a lot of the Inmarsat spectrum, and
That's an interesting thought. The diagram of the 9835 (the one labeled as
having the cosine ROM) also shows some sync logic associated with the select
lines steering the FSK and PSK registers. If that logic syncs the select lines
to the phase accumulator rollover, as you said, the slope of
Am 21.06.2011 21:03, schrieb KD0GLS:
On Jun 21, 2011, at 13:39, Chris Albertson wrote:
I used only 90 degrees of the table.
Yes, as did I and most implementations, but why a cosine quarter-table instead
of the more common sine? A quick look at the data sheets (and the waveforms in
the
-Original Message-
From: time-nuts-boun...@febo.com [mailto:time-nuts-
boun...@febo.com] On Behalf Of Ulrich Bangert
Sent: Tuesday, June 21, 2011 4:37 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] DDS'ery
Clever! At least for your spectral
On 06/21/2011 04:29 PM, Jim Lux wrote:
On 6/21/11 6:14 AM, dk...@arcor.de wrote:
There is an excellent article about cordic on
http://www.andraka.com/files/crdcsrvy.pdf
Yes..good explanation..
So, in the general case where you might want to rotate by an arbitrary
angle at each time step,
Group,
During my days of interest in antique radios, I learned that
the dielectric between aluminum plates was formed by passing
current in one direction to build up an oxide coating on the
plates, which became the dielectric. The thickness is directly
proportional to working voltage and
http://www.technewsworld.com/story/72712.html
Hardy
- Original Message -
From: time-nuts-requ...@febo.com
To: time-nuts@febo.com
Sent: Tuesday, June 21, 2011 10:09 PM
Subject: time-nuts Digest, Vol 83, Issue 72
Send time-nuts mailing list submissions to
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Hi Bill,
I agree with your forming information, as applied to older caps,
but not your temperature information. The 105C high temp caps
are just as happy, or unhappy really, with low temperatures as
the 85C caps. Basically the difference between the two is water.
The 85C caps have an
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