The LEA-6T carrier boards have all been claimed. If there is enough interest,
I might order more. Please contact me off-list if interested.
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No it has 4 x LTC2216 (single 16bit ADCs).
Bruce
On Sunday, 29 May 2016 4:06 AM, Bob Camp wrote:
HI
It’s been a while since I dug into a TimePod. Doesn’t it have two dual ADC’s in
it? You can select which
way you route the signals into the ADEV process.
Bob
> On May 28, 2016, at 11
HI
It’s been a while since I dug into a TimePod. Doesn’t it have two dual ADC’s in
it? You can select which
way you route the signals into the ADEV process.
Bob
> On May 28, 2016, at 11:04 AM, Bruce Griffiths
> wrote:
>
> One can just measure the TDEV performance.I can measure the TDEV per
So far, I’ve been configuring my 53220A for frequency measurements with a 500
msec gate time, and using the external reference and one input.
If instead I send the two devices into inputs A and B, and ask for the time
interval between the two and give that to Timelab, my results look quite a bit
One can just measure the TDEV performance.I can measure the TDEV performance at
10MHz later today if that's useful.It should be somewhat similar to the single
channel SDR instrument given there is no cancellation of most of the internal
ADC clock conditioning system noise.
Bruce
On Sunday
HI
It certainly sounds like the TDC 7200 is the way to go. Thanks for sharing !!
Bob
> On May 28, 2016, at 9:28 AM, Li Ang <379...@qq.com> wrote:
>
> Hi
>I got 5 samples of TDC7200 from TI a few months ago. I have made a board
> to test it with TDC-GP22 from ACAM. Actually it's a new board
On Sat, 28 May 2016 08:47:45 + (UTC)
Bruce Griffiths wrote:
> This SDR setup appears to have a higher PN (at least 2 ADC's per signal
> are required to achieve lower PN ) than a Timepod, however it appears
> to be better at measuring ADEV than a Timepod.
Yes, the spec'ed SNR of the ADS62P44
Hi
I got 5 samples of TDC7200 from TI a few months ago. I have made a board to
test it with TDC-GP22 from ACAM. Actually it's a new board of my frequency
counter. The CPU system is changed from MCU to a OrangePi board. The digital
part is still a Cyclone 4 FPGA.
Verilog: http://www.qsl.ne
On 5/27/16 6:58 PM, Hal Murray wrote:
bruce.griffi...@xtra.co.nz said:
All the filtering and down mixing is done in the digital domain.
Anitialiasing filters in front of the ADCs are also be required.
What sort of bandwidth is expected?
The usual trick with audio ADCs is to have a low cost a
On 5/27/16 5:17 PM, Bruce Griffiths wrote:
On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote:
Hi
Very interesting paper, thanks for sharing !!
One question:
In many DMTD (and single mixer) systems, a lowpass and high pass filter are
applied to the signal coming out of the mixer. This is do
On 5/27/16 6:15 PM, Bob Camp wrote:
Hi
On May 27, 2016, at 8:17 PM, Bruce Griffiths wrote:
On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote:
Hi
Very interesting paper, thanks for sharing !!
One question:
In many DMTD (and single mixer) systems, a lowpass and high pass filter are
appl
Hi
The Max V FPGA on the Bemicro card is pretty impressive. The gotcha is with the
Quartus
side of things. Altera is not willing to let you have the DSP stuff (NCO’s,
CIC’s, FIR’s) for free
the way Xilinx is.
Bob
> On May 28, 2016, at 4:47 AM, Bruce Griffiths
> wrote:
>
> A low pass filter
Hi
The normal process with a 10 Hz beat note in a DMTD is to have something like a
6 Hz two
pole high pass and a 15 Hz two pole lowpass after the mixer and before any zero
crossing stuff.
This is after down conversion, but before any demodulation. This of course is
based on the
fundamental a
Thank you for posting, but.. how does the optical strontium clock
described in the paper work?
Didn't they reach to use a flywheel frequency to regulate it before this?
Regards,
Ilia.
Il 27/05/2016 02:05, Mark Sims ha scritto:
https://www.osapublishing.org/optica/fulltext.cfm?uri=optica-3-6
A low pass filter will reduce the source broadband noise aliased into the ADC
output signal.
Using the LVDS ADC outputs rather than the CMOS outputs may help in reducing
noise generated on the board. NB the ADC performance is specified when the LVDS
outputs are used.
This SDR setup appears to
> As we are doing a similar desgin
> also using a Zynq 7010 I would appreciate if you could elaborate
> a bit what made the FPGA too small for your application.
It wasn't too small, I just had to think about just how much
filtering I was using. "It was a struggle" probably overstated the
situatio
The FPGA is probably adequate (if it has LVDS inputs), but a dual single chip
ADC is also required.
Bruce
On Saturday, 28 May 2016 5:05 PM, Bob Stewart wrote:
Hi Bruce,
What about the BeMicroCV-A9 that Scotty Cowling has been recommending in QEX?
It has a Cyclone V SoC FPGA running
I ordered 10 of those bare carrier boards that Keenan mentioned for the LEA-6T
modules:
http://openbsc.osmocom.org/trac/wiki/osmo-lea6t-gps
I will be using 4 of them. That leaves 6 available if anybody is interested.
Contact me off list. Price would be $10 each, shipped in the US (I paid extra
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