10:39 AM
To: rich...@karlquist.com; Discussion of precisetime and frequency
measurement
Subject: Re: [time-nuts] 10MHz to 80MHz frequency multiplier suggestions
An MSA08 saturated with 10MHz input give a comb with +2.5dBM @80Mhz(see
screenshot). You have only to filter this frequency to clean the o
An MSA08 saturated with 10MHz input give a comb with +2.5dBM @80Mhz(see
screenshot). You have only to filter this frequency to clean the output
spectrum.
Regards, Luciano
Luciano P. S. Paramithiotti
IZ5JHJ
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> Whilst the close in phase noise of the ADC used in the TSC5115 may be
> comparable with that of a 74AC04 the phase noise floor of such ADCs is
> degraded when clocked by a 74AC04...
> In particular such ADCs have been be used to measure the jitter of
> various logic families by using devices fro
Hi
Another way to filp that around is that the same ADC's begin to degrade if the
broadband phase noise isn't at least in the 150's. With an 18 db penalty for
multiplying, that puts you into the 170's for phase noise out of the TBolt.
Even if the TBolt OCXO is that good (doubtful) building a mu
Whilst the close in phase noise of the ADC used in the TSC5115 may be
comparable with that of a 74AC04 the phase noise floor of such ADCs is
degraded when clocked by a 74AC04:
http://www.analog.com/static/imported-files/seminars_webcasts/High%20Speed%20System%20Applications%20%28PDF%29/HS%20Sys
Gerhard Hoffmann wrote:
Am 31.01.2011 22:48, schrieb dave powis:
Hi Chris,
Yes, of course the multiplication plan is a little different, but in
the circuit
I linked the basic multiplier is a doubler from 10 to 20MHz, that
produces a
comb of 2f products. The design as presented has BPF's to s
>
> Before one can conclude such a solution is adequate one needs to know
> the ADC requirements for clock jitter.
> If the ADC is a high resolution pipelined ADC like those available from
> AD and LTC then such a solution will degrade the performance
> significantly.
> These ADCs require clock cy
Am 31.01.2011 22:48, schrieb dave powis:
Hi Chris,
Yes, of course the multiplication plan is a little different, but in
the circuit
I linked the basic multiplier is a doubler from 10 to 20MHz, that
produces a
comb of 2f products. The design as presented has BPF's to select the 5th
harmonic, a
I was contemplating the same thing. I fed the output to a bifilar transformer
and
diode doubler and got good results. I have to add an amp and double it again
twice
more. It is still on breadboard. The object was to multiply the error 8x and
compare.
Probably a PLL locking to 80 Mhz will retai
dave powis wrote:
> I'm well aware that time nuts is probably the very worst reflector on
> which to
> post a 'simple' solution! However, it was, as I thought I had made
> abundantly
Although the schematic looks "simple" in some sense, these circuits
are a can of worms to tune up optimally and ar
I suggest to ask LTC first for what is required. Personally I think one
of the clock multipliers for SONET etc should be enough. silabs have
several parts, others too.
If I remember correctly, I've seen a App Note describing oscillator
requirements at LTC website.
- Henry
Elio Corbolante s
Rick Karlquist wrote:
>You will be much happier with three doublers in cascade.
>Try copying the HP8662 doublers as an example. We also
>did this in the HP5071 (no I don't have schematics handy
>at this time).
I searched for the 8662/3 schematics, but I only found low resolution PDFs.
Even for the
cise time and frequency measurement
Sent: Monday, 31 January, 2011 20:35:57
Subject: Re: [time-nuts] 10MHz to 80MHz frequency multiplier suggestions
On Mon, Jan 31, 2011 at 11:06 AM, dave powis wrote:
> Have you seen http://www.timeok.it/files/10_to_100_mhz_multiplier.pdf ? ...
> Although t
On Mon, Jan 31, 2011 at 11:06 AM, dave powis wrote:
> Have you seen http://www.timeok.it/files/10_to_100_mhz_multiplier.pdf ? ...
> Although the design is for 100MHz, changing the band pass filters to 80MHz
> will give you that as your output,
80Mhz sounds close to 100Mhz. But look at the prime
dave powis wrote:
> Have you seen http://www.timeok.it/files/10_to_100_mhz_multiplier.pdf ?
> You
> should probably both take a look at this solution as a start - maybe not
> Dave G4HUP
>
You will be much happier with three doublers in cascade.
Try copying the HP8662 doublers as an example. We al
73,
Dave G4HUP
http://g4hup.com
From: Chris Albertson
To: Discussion of precise time and frequency measurement
Sent: Monday, 31 January, 2011 18:27:06
Subject: Re: [time-nuts] 10MHz to 80MHz frequency multiplier suggestions
I'd like to hear from one of the e
Hi Elio,
On 31/01/11 16:46, Elio Corbolante wrote:
I'd like to convert the 10MHz output of a Thunderbolt to 80MHz: it should be
used as a 3.3V clock for an A/D converter.
Even if I have already taken a look to documentation from KO4BB and Wenzel
regarding frequency multiplier,
I'm asking if you
Elio Corbolante wrote:
Chris Albertson wrote:
Does a A/D converter really need a GPS controlled clock?
In this case where exact precision is not required you could use a
4046 phase lock loop chip. You set the VCO for 80Mhz then divide that
by 8 and feed it back to the chip.[...]
If you go th
: Monday, 31 January, 2011 18:27:06
Subject: Re: [time-nuts] 10MHz to 80MHz frequency multiplier suggestions
I'd like to hear from one of the experts about which method has the
least noise a PLL or a multiplier. The PLL could have a very good
VCO, it could be a crystal oscillator that is stee
I have no first hand knowledge of this, but from places where I've worked, the
general consensus is to "pull" a resonant circuit. Basically a varactor diode
pulling a crystal in a PLL.
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I'd like to hear from one of the experts about which method has the
least noise a PLL or a multiplier. The PLL could have a very good
VCO, it could be a crystal oscillator that is steered by the phase
detector. The The multiplier could introduce noise in the mixers or
other active parts. I think
Chris Albertson wrote:
> Does a A/D converter really need a GPS controlled clock?
>In this case where exact precision is not required you could use a
>4046 phase lock loop chip. You set the VCO for 80Mhz then divide that
>by 8 and feed it back to the chip.[...]
>If you go this route, I think the 80
Does a A/D converter really need a GPS controlled clock?
In this case where exact precision is not required you could use a
4046 phase lock loop chip. You set the VCO for 80Mhz then divide that
by 8 and feed it back to the chip. The chip will compare that 10Mhz
signal with the T-Bolt's 10Mhz sig
I'd like to convert the 10MHz output of a Thunderbolt to 80MHz: it should be
used as a 3.3V clock for an A/D converter.
Even if I have already taken a look to documentation from KO4BB and Wenzel
regarding frequency multiplier,
I'm asking if you have some more references or even better, some schemat
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