Bruce, et al,
"Metastability" was mentioned again recently - I think I read some
messages earlier this year, but can't remember if they were current, or
in the archive, and can't now quickly find them. I think it has to do
with latches getting into an undeterminable state when asynchronous
i
Hi guys,
I noticed Hal's pointer to Johnson and Graham's HSDD
in the Metastability thread, and wondered if anybody here
has seen Johnson's DVD on the subject:
http://www.sigcon.com/SiLab/filmsNow.htm#metastability
Yasi
_
Like
If it hasn't yet been mentioned, another great metastability resource :
_http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm_
(http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm)
Brian
** See what's free at http://www.a
You need to have a two stage register, allowing one clock period
for the first stage to come out of metastability. This of course
delays the signal to be synchronized by a clock period. In an
attempt to get around this delay, you sometimes see a series of
registers in cascade clocked at slightly
Metastability is simple after you get it. Lots of people, including some who
should know better get it wrong.
The best real world analogy that I know of is rolling a ball over a bump. If
the ball has lots of energy, it goes over over the bump and down the other
side. If it doesn't have much
> You need to have a two stage register, allowing one clock period for
> the first stage to come out of metastability. This of course delays
> the signal to be synchronized by a clock period.
Yup. The delay is unavoidable. The only thing you can do is trade off delay
vs MTBF.
> In an attemp
Thank you both, and particularly Hal, for your explanations - I think
I get it now. It's great to have you experts online!
Thanks again,
Peter
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Hal Murray wrote:
>> You need to have a two stage register, allowing one clock period for
>> the first stage to come out of metastability. This of course delays
>> the signal to be synchronized by a clock period.
>>
>
> Yup. The delay is unavoidable. The only thing you can do is trade off d
S/LS logic was introduced in the mid 70's, F/AS/ALS around 1980, HC was
early 80's. By the third 7400 generation (F/AS/ALS) the problem was
well known with parameters available and the logic fairly hard to it.
On 3/25/13 2:56 PM, Attila Kinali wrote:
On Mon, 25 Mar 2013 14:03:23 -0400
David
On Mon, Mar 25, 2013 at 12:45 PM, David McGaw wrote:
> S/LS logic was introduced in the mid 70's, F/AS/ALS around 1980, HC was
> early 80's. By the third 7400 generation (F/AS/ALS) the problem was well
> known with parameters available and the logic fairly hard to it
I think this is all moot bec
Both edges of the 24MHz clock gating pulse are asynchronous with respect
to the signal being gated.
Metastability can result with clock pulse widths that lie within a
critical range.
Bruce
Chris Albertson wrote:
On Mon, Mar 25, 2013 at 12:45 PM, David McGaw wrote:
S/LS logic was introdu
t and you probably should look at things again...
Bob
-Original Message-
From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On
Behalf Of Bruce Griffiths
Sent: Monday, March 25, 2013 4:38 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts]
bably should look at things again...
>
> Bob
>
> -Original Message-
> From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On
> Behalf Of Bruce Griffiths
> Sent: Monday, March 25, 2013 4:38 PM
> To: Discussion of precise time and frequency mea
n1...@alum.dartmouth.org said:
> S/LS logic was introduced in the mid 70's, F/AS/ALS around 1980, HC was
> early 80's. By the third 7400 generation (F/AS/ALS) the problem was well
> known with parameters available and the logic fairly hard to it.
The problem is well understood in the right circl
>> minute will mess up the loop. In the second case, you will never notice the
>> issue.
>>
>> Of course, boost the clock, change the logic family, mix logic families,
>> fiddle this or that and you probably should look at things again...
>>
>> Bob
>>
Hi
The reason you don't see MTBF's is that they are indeed hard to find. Even the
formulas that come up with them are not particularly easy to deal with. What
they very much want you to do is to spend big bucks on the analysis program and
the data to drive it.
To put some numbers on it:
At 3
On Mon, 25 Mar 2013 14:56:25 -0700, Hal Murray
wrote:
>
>n1...@alum.dartmouth.org said:
>> S/LS logic was introduced in the mid 70's, F/AS/ALS around 1980, HC was
>> early 80's. By the third 7400 generation (F/AS/ALS) the problem was well
>> known with parameters available and the logic fairly h
> Both edges of the 24MHz clock gating pulse are asynchronous with respect
> to the signal being gated.
> Metastability can result with clock pulse widths that lie within a
> critical range.
>
> Bruce
I don't disagree with your statement above, but my question was -- does it
matter in a GPSDO;
On Mon, Mar 25, 2013 at 3:02 PM, Bob Camp wrote:
> Hi
>
> In normal operation, the counter is clocking back and forth across the 1024 /
> 24,000,000 boundary. It has to do this for the control loop to "see"
> anything. Put another way, if it's always 1024 / 24,000,000 the loop does
> nothing at
On Mon, Mar 25, 2013 at 3:41 PM, Chris Albertson
wrote:
>> In normal operation, the counter is clocking back and forth across the 1024
>> / 24,000,000 boundary. It has to do this for the control loop to "see"
>> anything. Put another way, if it's always 1024 / 24,000,000 the loop does
>> nothi
Tom Van Baak wrote:
Both edges of the 24MHz clock gating pulse are asynchronous with respect
to the signal being gated.
Metastability can result with clock pulse widths that lie within a
critical range.
Bruce
I don't disagree with your statement above, but my question was -- does it
matt
time-nuts-boun...@febo.com
Date: Mon, 25 Mar 2013 18:02:33
To: Discussion of precise time and frequency measurement
Reply-To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Metastability (was Brooks Shera)
Hi
In normal operation, the counter is clocking bac
li...@rtty.us said:
> If the data is changing as the clock fires, the flip flop oscillates rather
> than goes to a single state.
It may not oscillate. Some sit at halfway and then wander off, slowly at
first but with an exponential speedup.
The usual way to describe metastability is how much l
On Mon, Mar 25, 2013 at 11:16 PM, Tom Van Baak wrote:
>> Both edges of the 24MHz clock gating pulse are asynchronous with respect
>> to the signal being gated.
>> Metastability can result with clock pulse widths that lie within a
>> critical range.
>>
>> Bruce
>
> I don't disagree with your statem
Hi
The worst case (this time) are errors in the bottom 5 bits. The software will
treat them as valid data. That assumes things stay simple. You are looking a
counter that wraps around a lot of times….
Bob
On Mar 26, 2013, at 7:33 AM, Javier Serrano
wrote:
> On Mon, Mar 25, 2013 at 11:16 PM,
); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]
In my Brooks Shera style LPRO rubidium controller I am using
the same HC4046 input conditioner and divide down counter on
the oscillator and HC4046 phase detector interrupting the PIC
as used in the original design. The phase detector
); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]
Richard H McCorkle wrote:
>With the discussions here on metastable states in TIC
> counters, I am asking the experts on the list for their
> opinion if the performance of this design would improve
> by adding a shift register syn
IL PROTECTED]
> [mailto:[EMAIL PROTECTED] Im Auftrag von Richard H McCorkle
> Gesendet: Donnerstag, 19. Juli 2007 09:09
> An: time-nuts@febo.com
> Betreff: [time-nuts] Metastability in a 100 MHz TIC
>
>
> ); SAEximRunCond expanded to false
> Errors-To:
> time-nuts-boun
); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]
Ulrich Bangert wrote:
> Richard,
>
> metastability is an effect that happens when the setup times of an
> d-flipflop are not met. This can happen (with a certain statistical
> likelyhood) when the sources of the data input and the clo
); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]
> Question: Since you are comparing
> TWO oscillators by means of an THIRD oscillator (the tic's time base),
> does the tic's time base stability influence your measurement results or
> not?
Partly yes, for tau < 1 second.
Mostly no,
for some older hobbyists.
Thanks again,
Richard
Original Message
-
Subject: Re: [time-nuts] Metastability in a 100 MHz TIC
From:"Tom Van Baak" <[EMAIL PROTECTED]>
Date:Fri, July 20, 2007 6:57 am
To:
r hobbyists.
Thanks again,
Richard
Original Message
-----
Subject: Re: [time-nuts] Metastability in a 100 MHz TIC
From:"Tom Van Baak" <[EMAIL PROTECTED]>
Date:Fri, July 20, 2007 6:57 am
To: "Discu
hobbyist. Age can do bad things
> to the eyes and hands that make surface mount components and high
> density IC pinouts hard to deal with for some older hobbyists.
>
> Thanks again,
> Richard
>
> Original Message
> --
); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]
Tom Van Baak wrote:
> Richard,
>
> A 1.6 us window mean you have almost no issues with
> the accuracy or stability of your 100 MHz sample clock.
> 10 ns out of 1.6 us is 1/2 percent; clock counts won't
> exceed 160; a quartz timebase
); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]
Richard,
Ah, I see now. Sorry. You are adding 120 TIC values together,
dividing by 120 to get one mean TI value.
You are also, independently, adding 120 sawtooth corrections
together and dividing by 120 to get one mean correction va
); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]
Bruce,
I like your point about the random quantization error in the
sawtooth. Yes, that would help the noise by a few dB.
On the other hand it would also seem the 10 ns resolution
of the TIC is the limiting factor (by an order of ma
); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]
Tom
Tom Van Baak wrote:
> Bruce,
>
> I like your point about the random quantization error in the
> sawtooth. Yes, that would help the noise by a few dB.
>
> On the other hand it would also seem the 10 ns resolution
> of the TIC is th
From: "Tom Van Baak" <[EMAIL PROTECTED]>
Subject: Re: [time-nuts] Metastability in a 100 MHz TIC
Date: Fri, 20 Jul 2007 17:10:45 -0700
Message-ID: <[EMAIL PROTECTED]>
> ); SAEximRunCond expanded to false
> Errors-To: [EMAIL PROTECTED]
>
> Bruce,
>
has been shown to
work in some cases.
Alan G3NYK
- Original Message -
From: Dr Bruce Griffiths <[EMAIL PROTECTED]>
To: Tom Van Baak <[EMAIL PROTECTED]>; Discussion of precise time and
frequency measurement
Sent: 21 July 2007 00:16
Subject: Re:
); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]
Alan Melia wrote:
> Bruce I find this an interesting thread...one maybe naive thought..
> "it would be nice to have a"too-good" stability on the 100MHz TIC but
> detracts from the averaging" (My interpretation), this almost su
> The simpler and cheaper D
> flipflop precedence detector used together with hardware sawtooth
> correction has far higher resolution. It also has the advantage of not
> requiring any high frequency clocks.
>
> Bruce
Since Rick & Dr TAC brought it up some months ago, does
anyone have measurem
Tom Van Baak wrote:
The simpler and cheaper D
flipflop precedence detector used together with hardware sawtooth
correction has far higher resolution. It also has the advantage of not
requiring any high frequency clocks.
Bruce
Since Rick & Dr TAC brought it up some months ago, does
anyo
Hal wrote:
>
>Back in those days, there was a lot of activity in designing kludgey
circuits
>to "fix" metastability. I could usually find the flaw. It got boring after
>a while. The classic was a circuit to detect metastability and reset the
FF.
>That reset signal would sometimes have runt
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