: Donnerstag, 19. Juli 2007 09:09
An: time-nuts@febo.com
Betreff: [time-nuts] Metastability in a 100 MHz TIC
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[EMAIL PROTECTED]
In my Brooks Shera style LPRO rubidium controller
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Ulrich Bangert wrote:
Richard,
metastability is an effect that happens when the setup times of an
d-flipflop are not met. This can happen (with a certain statistical
likelyhood) when the sources of the data input and the clock
with for some older hobbyists.
Thanks again,
Richard
Original Message
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Subject: Re: [time-nuts] Metastability in a 100 MHz TIC
From:Tom Van Baak [EMAIL PROTECTED]
Date:Fri, July 20, 2007 6:57 am
To: Discussion of precise
Original Message
-
Subject: Re: [time-nuts] Metastability in a 100 MHz TIC
From:Tom Van Baak [EMAIL PROTECTED]
Date:Fri, July 20, 2007 6:57 am
To: Discussion of precise time and frequency measurement
time-nuts@febo.com
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Tom
Tom Van Baak wrote:
Bruce,
I like your point about the random quantization error in the
sawtooth. Yes, that would help the noise by a few dB.
On the other hand it would also seem the 10 ns resolution
of the TIC is the
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Alan Melia wrote:
Bruce I find this an interesting thread...one maybe naive thought..
it would be nice to have atoo-good stability on the 100MHz TIC but
detracts from the averaging (My interpretation), this almost suggests
The simpler and cheaper D
flipflop precedence detector used together with hardware sawtooth
correction has far higher resolution. It also has the advantage of not
requiring any high frequency clocks.
Bruce
Since Rick Dr TAC brought it up some months ago, does
anyone have measurements
Tom Van Baak wrote:
The simpler and cheaper D
flipflop precedence detector used together with hardware sawtooth
correction has far higher resolution. It also has the advantage of not
requiring any high frequency clocks.
Bruce
Since Rick Dr TAC brought it up some months ago, does
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In my Brooks Shera style LPRO rubidium controller I am using
the same HC4046 input conditioner and divide down counter on
the oscillator and HC4046 phase detector interrupting the PIC
as used in the original design. The phase
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Richard H McCorkle wrote:
With the discussions here on metastable states in TIC
counters, I am asking the experts on the list for their
opinion if the performance of this design would improve
by adding a shift register
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