Alberto,
I have been reading the time-nuts archives and ran across a Feb 25, 2006
post where you mention you coded a GPSDO for an Atmel AT90s8535. Is
that code still available and could I please get a copy of it. Also, if
you have a schematic I would like to see same if possible.
Thanks,
and frequency measurement
Subject: Re: [time-nuts] Thought experiment on a low cost timing board
SNIP
Also I think Brooks Shera keeps a copy of the code at:
http://www.rt66.com/~shera/index_fs.htm
Unfortunately there is only the hex list of the pic code.
As I would like to experiment as well
February 2006 14:11
To: Tom Van Baak; Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Thought experiment on a low cost timing board
SNIP
Also I think Brooks Shera keeps a copy of the code at:
http://www.rt66.com/~shera/index_fs.htm
Unfortunately
Old message:
Von: Alberto di Bene [EMAIL PROTECTED]
An: Discussion of precise time and frequency measurement
time-nuts@febo.com
Betreff: Re: [time-nuts] Thought experiment on a low cost timing board
Datum: Sat, 25 Feb 2006 15:37:02 +0100
Arnold Tibus wrote:
Unfortunately
Hi everyone,
Poul-Henning Kamp wrote:
You don't even need 32bits for that:
http://phk.freebsd.dk/pubs/timecounter.pdf
And doing it in hardware would be more expensive than in software, hardware
access is much slower than memory access.
How about taking one of the bigger FPGA's,
Paul Boven wrote:
Hi everyone,
Poul-Henning Kamp wrote:
You don't even need 32bits for that:
http://phk.freebsd.dk/pubs/timecounter.pdf
And doing it in hardware would be more expensive than in software, hardware
access is much slower than memory access.
How about taking
On Feb 26, 2006, at 6:24 PM, Paul Boven wrote:
Hi everyone,
Poul-Henning Kamp wrote:
You don't even need 32bits for that:
http://phk.freebsd.dk/pubs/timecounter.pdf
And doing it in hardware would be more expensive than in software,
hardware
access is much slower than memory
On Feb 26, 2006, at 6:37 PM, David Andersen wrote:
Paul's own experiments showed, a Soekris box with
^^^
Poul's. Apologies, my fingers got ahead of my brain.
-Dave
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Hal Murray wrote:
What prompted this in the first place was the horrible temperature
sensitivity my soekris boxes exhibit - I can only keep them to within
10us of the gps 95% of the time and the occasional 100us excursion is
not uncommon. I want to be stable to the limit of the gps I'm
In message [EMAIL PROTECTED], John Pettitt writes:
I read the work phk did (http://phk.freebsd.dk/soekris/pps/) and came up
with the following product idea.
The spec:
PCI 3.3v board with:
10Mhz OCXO (provision for external clock source?)
Uart (serial is an endangered on many PC's)
From: Poul-Henning Kamp [EMAIL PROTECTED]
Subject: Re: [time-nuts] Thought experiment on a low cost timing board
Date: Sat, 25 Feb 2006 10:45:54 +
Message-ID: [EMAIL PROTECTED]
Poul-Henning,
Another thing you have to be aware of is something called
'meta-stability' when you latch a signal
My solution was to replace the 'HC390 change with the elegant
PIC-based divider chain invented by Tom van Baak. This uses the 10 MHz
signal as the PIC's clock, and the tight code based on a fixed number
of wait states makes a fully synchronous divider. I was unable to
measure ANY
Arnold Tibus wrote:
Unfortunately there is only the hex list of the pic code.
As I would like to experiment as well with this modification
and try to change some parameters to fit my LPRO
and some different OCXOs I own,
is there a way to get the commented source code of it?
I
In message [EMAIL PROTECTED], Magnus Danielson writes:
Consider adding a D/A converter for tweaking OCXO. Using the two-tier
trick which SRS uses in the PRS10 may be a good and cheap way.
two-tier trick? Lacking the PRS10 schematics/service manuals...
They have two 12 bit D/As which are
They have two 12 bit D/As which are summed through a 1:1000 network to
give around 20 bits of effective resolution at the cost of some
discontinuities.
Because the ratio is only a quarter of the full ratio of the
individual D/A's, they can always center the interresting range in the
lower
PCI 3.3v board with:
10Mhz OCXO (provision for external clock source?)
Uart (serial is an endangered on many PC's)
Free running counter driven from the OCXO and readable by PC
inputs to latch the counter (how many?) with the latched result
also readable (for PPS)
I've been
What prompted this in the first place was the horrible temperature
sensitivity my soekris boxes exhibit - I can only keep them to within
10us of the gps 95% of the time and the occasional 100us excursion is
not uncommon. I want to be stable to the limit of the gps I'm using
- for no
At 3:50 PM -0800 2/25/06, John Pettitt wrote:
I had several goals in mind when I asked the initial question:
1) a low cost high stability ntp stratum 1 clock board - something that
when added to a sub $100 gps would yield a really stable time source for
ntp. To do this it really needs to let the
Hello Poul-Henning,
how does SRS handle OCXO aging?
If the fine DAC only has 1:1000 of their 12-bit coarse DAC, and the EFC
range is +-20Hz, then the LSB DAC can only control about 2E-09 or so over its
full range if my math is correct.
Good OCXO's (e.g. MTI) crystals usually age between
John Pettitt [EMAIL PROTECTED] wrote:
Tim Shoppa wrote:
My gut feeling: back up a little bit. Figure out how to do what you
want without a PCI bus, without gold fingers, without BGA's, etc.
I had several goals in mind when I asked the initial question:
1) a low cost high stability
From: Poul-Henning Kamp [EMAIL PROTECTED]
Subject: Re: [time-nuts] Thought experiment on a low cost timing board
Date: Sat, 25 Feb 2006 19:11:15 +
Message-ID: [EMAIL PROTECTED]
In message [EMAIL PROTECTED], Magnus Danielson writes:
Consider adding a D/A converter for tweaking OCXO
In message [EMAIL PROTECTED], Hal Murray writes:
One of the things I was thinking about putting in the FPGA was a pair of 32
bit counters for implementing the unix date/time directly.
You don't even need 32bits for that:
http://phk.freebsd.dk/pubs/timecounter.pdf
And doing it in
In message [EMAIL PROTECTED], [EMAIL PROTECTED] writes:
Good OCXO's (e.g. MTI) crystals usually age between 3E-09 to 5E-010 per day
as per their spec.
They use this for the OCXO which is steered by the Rb cell, so they have
a very high feedback frequency, so I think they just live with the
The TAPR Reflock II board (designed by Luis Cupido) is shipping now and
will discipline a VCXO to 1pps, or to other frequencies. I'm traveling
now and don't have the exact URL handy, but www.tapr.org will have a link.
I've spoken with Luis about using the Reflock to synthesize an
appropriate
I have done several GPSDOs using the NAVMAN receiver, so I add a few
comments to the discussion:
1. Both the G3RUH
([1]http://www.jrmiller.demon.co.uk/projects/ministd/frqstd.htm) and
I2PHD ([2]http://gpsdo.i2phd.com/) designs use 74HC390 divider chips;
I also tried them. What I
From: Tom Clark, K3IO (ex W3IWI) [EMAIL PROTECTED]
I have done several GPSDOs using the NAVMAN receiver, so I add a few
comments to the discussion:
1. Both the G3RUH
([1]http://www.jrmiller.demon.co.uk/projects/ministd/frqstd.htm) and
I2PHD ([2]http://gpsdo.i2phd.com/) designs use 74HC390
So does the basic idea make sense? More importantly can somebody opine
on if it's possible to use a 1PPS to discipline an OCXO (I've seen
designs to it from a 10KHz signal for sale on eBay)) -
Yes, many devices, both professional and amateur,
use a precise 1PPS signal to discipline Qz, Rb,
Tom Van Baak wrote:
I'm curious about the 10 kHz signal. Can you send
me a pointer to it? Usually 1 Hz is good enough and
in practice most GPSDO use an averaging algorithm
that is more akin to 0.01 Hz to 0.001 Hz.
http://gpsdo.i2phd.com/
73 Alberto I2PHD
Tom Van Baak wrote:
I'm curious about the 10 kHz signal. Can you send
me a pointer to it? Usually 1 Hz is good enough and
in practice most GPSDO use an averaging algorithm
that is more akin to 0.01 Hz to 0.001 Hz.
/tvb
See http://www.jrmiller.demon.co.uk/projects/ministd/frqstd.htm
Silabs has some 8051 cored chips that run at 100 MHz with close to 1
instruction/cycle. I use them (not for timing), they really are speedy.
The C8051C123 runs at 100 MHz with 2 built-in DACs (and a bunch of other
goodies, such as 128kB of flash, 8k of RAM, 2 x 8 input ADCs, one 8
bits/500ks/s,
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