If you walk the differential data and clock inputs of an NB7V52 CML
flipflop across one another in time, the equivalent jitter is below 20
fs RMS. That's what we're measuring, but our test rig may well dominate
the jitter, so the flop is probably better.
We're using this to test the jitter of
Hello fellow time nuts,
Have a project here with an OCXO from Vectron at 38.88MHz being the
"jitter reference" for a DSP based PLL.
The Vectron part has a little bit of close-in phase noise below 12kHz
of BW. Is there a way to filter this, say by driving an external
(temperature stabilize
> Chris
> The biggest problem with the OCXO is probably that it has a square
> wave output.
> With careful design it is possible to achieve a jitter of a few
> tens of femtosec for a logic level output from a limiter, but the
> OCXO designers are unlikely to have used such a limit
Thus a DDMTD using NB7V52's as the mixers should have useful performance
Bruce
> On 14 April 2018 at 03:54 John Larkin wrote:
>
>
> If you walk the differential data and clock inputs of an NB7V52 CML
> flipflop across one another in time, the equivalent jitter is below 20
> fs RMS. That's w
John,
How where these measurements done?
Also, it looks like you have a systematic component in there, about 80
fs guestimating from the plot creating essentially two tracks up the
slope that is the tell-tale of a sinuoid phase modulation of some source.
Considering the temperature stability that
On Fri, 13 Apr 2018 08:54:41 -0700
John Larkin wrote:
> If you walk the differential data and clock inputs of an NB7V52 CML
> flipflop across one another in time, the equivalent jitter is below 20
> fs RMS. That's what we're measuring, but our test rig may well dominate
> the jitter, so the f
Hi, Magnus,
We did a little PC board that has two Analog Devices CML comparators
that feed the flop.
https://www.dropbox.com/s/05ti1c57eush0uq/99S394A.pdf?dl=0
An external DAC tweaks the VBIAS voltage to slew the edge times across
one another, and an external ADC looks at the averaged flop
Hi,
On 04/14/2018 06:45 PM, John Larkin wrote:
> Hi, Magnus,
>
> We did a little PC board that has two Analog Devices CML comparators
> that feed the flop.
>
> https://www.dropbox.com/s/05ti1c57eush0uq/99S394A.pdf?dl=0
>
> An external DAC tweaks the VBIAS voltage to slew the edge times across
On 4/15/2018 2:17 PM, Magnus Danielson wrote:
Hi,
On 04/14/2018 06:45 PM, John Larkin wrote:
Hi, Magnus,
We did a little PC board that has two Analog Devices CML comparators
that feed the flop.
https://www.dropbox.com/s/05ti1c57eush0uq/99S394A.pdf?dl=0
An external DAC tweaks the VBIAS v
Chris Mack / N1SKY skrev:
> Hello fellow time nuts,
>
> Have a project here with an OCXO from Vectron at 38.88MHz being the
> "jitter reference" for a DSP based PLL.
>
> The Vectron part has a little bit of close-in phase noise below 12kHz
> of BW. Is there a way to filter this, say by driv
Hey Magnus,
This is a good idea for testing.. I have Howard Johnson's book for
"high speed digital design (a handbook of black magic)" which shows
some circuits with varactors on the transmission line with some ECL
gates creating a variable delay based on an analogue voltage... maybe
that
Chris,
Chris Mack / N1SKY skrev:
> Hey Magnus,
>
> This is a good idea for testing..
Applying jitter frequencies for jitter tolerance testing is standard
stuff and needs to be done. Jitter tolerance curves match up with MTIE
tolerance curves very neatly.
> I have Howard Johnson's book for
Magnus
For examples of the use of crystals in filters for cleaning up the
output of a crystal oscillator look at the circuit schematics for some
of the early crystal frequency standards.
Crystal filters were used quite liberally in some of these to clean up
the outputs.
However it may be necessary
Bruce Griffiths skrev:
> Magnus
>
> For examples of the use of crystals in filters for cleaning up the
> output of a crystal oscillator look at the circuit schematics for some
> of the early crystal frequency standards.
> Crystal filters were used quite liberally in some of these to clean up
> the
Magnus
Magnus Danielson wrote:
> Bruce Griffiths skrev:
>
>> Magnus
>>
>> For examples of the use of crystals in filters for cleaning up the
>> output of a crystal oscillator look at the circuit schematics for some
>> of the early crystal frequency standards.
>> Crystal filters were used quite
>> This is a good idea for testing..
>
> Applying jitter frequencies for jitter tolerance testing is standard
> stuff and needs to be done. Jitter tolerance curves match up with MTIE
> tolerance curves very neatly.
>
Of course, here is the weird part... It's not SONET; but it is a chip
that can
Bruce Griffiths skrev:
> Chris
>
> Chris Mack / N1SKY wrote:
This is a good idea for testing..
>>> Applying jitter frequencies for jitter tolerance testing is standard
>>> stuff and needs to be done. Jitter tolerance curves match up with MTIE
>>> tolerance curves very neatly.
>>>
Hej Bruce,
Bruce Griffiths skrev:
> Magnus
>
> Magnus Danielson wrote:
>> Bruce Griffiths skrev:
>>
>>> Magnus
>>>
>>> For examples of the use of crystals in filters for cleaning up the
>>> output of a crystal oscillator look at the circuit schematics for some
>>> of the early crystal frequenc
Chris
Chris Mack / N1SKY wrote:
>>> This is a good idea for testing..
>>>
>> Applying jitter frequencies for jitter tolerance testing is standard
>> stuff and needs to be done. Jitter tolerance curves match up with MTIE
>> tolerance curves very neatly.
>>
>>
>
> Of course, here is the
On Apr 8, 2009, at 8:02 PM, Bruce Griffiths wrote:
> Unless you are prepared to place the crystals in an oven with the
> temperature regulated tightly and carefully tune the filter
> periodically
> then using a crystal filter (or any passive filter with a sufficiently
> narrow bandwidth to cle
Chris Mack / N1SKY wrote:
> On Apr 8, 2009, at 8:02 PM, Bruce Griffiths wrote:
>
>
>
>> Unless you are prepared to place the crystals in an oven with the
>> temperature regulated tightly and carefully tune the filter
>> periodically
>> then using a crystal filter (or any passive filter with a
On Apr 8, 2009, at 8:50 PM, Bruce Griffiths wrote:
>>
> Chris
>
> If you divide the output down to ~38MHz using a noiseless divider then
> the performance is 20dB or more worse than can be achieved with a good
> ~38MHz crystal oscillator.
>
Ah, this would work, but there is a synchronization aspe
Chris
Now we have a more complete picture of what you are trying to do our
suggestions will perhaps be a little more useful.
Cleaning up a marginal OCXO is quite complex and probably more
expensive than obtaining an OCXO or other reference that has lower noise.
Is it in fact possible to just sub
Thanks Bruce,
The 12kHz is a figure for the DSP PLL and how they measure it
(starting at 12kHz usually for jitter over BW measurements) I
haven't touched SONET since 1997 and this may be a SONET spec?
I am using the simulator software for the LMK04000 series to see what
jitter is for th
Chris
The biggest problem with the OCXO is probably that it has a square wave
output.
With careful design it is possible to achieve a jitter of a few tens of
femtosec for a logic level output from a limiter, but the OCXO designers
are unlikely to have used such a limiter.
To produce a sinewave ou
> The incoming clock source (master house clock) to this box / design
> of interest is in another rack mount box external to this design on
> the other side of the room and is anywhere from 44.1kHz up to a 10MHz
> Rubidium (see also http://www.antelopeaudio.com). This clock source
> on the
Bruce Griffiths skrev:
> Hej Magnus
>
> Magnus Danielson wrote:
>> Hej Bruce,
>>
>> Bruce Griffiths skrev:
>>
>>> Magnus
>>>
>>> Magnus Danielson wrote:
>>>
Bruce Griffiths skrev:
> Magnus
>
> For examples of the use of crystals in filters for cleaning
Hej Magnus
Magnus Danielson wrote:
> Bruce Griffiths skrev:
>
>> Hej Magnus
>>
>> Magnus Danielson wrote:
>>
>>> Hej Bruce,
>>>
>>> Bruce Griffiths skrev:
>>>
>>>
Magnus
Magnus Danielson wrote:
> Bruce Griffiths skrev:
>
>
At 20:59 -0700 08-04-2009, Tom Van Baak wrote:
> > The incoming clock source (master house clock) to this box / design
>> of interest is in another rack mount box external to this design on
>> the other side of the room and is anywhere from 44.1kHz up to a 10MHz
>> Rubidium (see also http://
At 22:03 -0400 08-04-2009, Chris Mack / N1SKY wrote:
>On Apr 8, 2009, at 8:50 PM, Bruce Griffiths wrote:
>>>
>> Chris
>>
>> If you divide the output down to ~38MHz using a noiseless divider then
>> the performance is 20dB or more worse than can be achieved with a good
>> ~38MHz crystal oscillat
On Apr 8, 2009, at 11:59 PM, Tom Van Baak wrote:
>> The incoming clock source (master house clock) to this box / design
>> of interest is in another rack mount box external to this design on
>> the other side of the room and is anywhere from 44.1kHz up to a 10MHz
>> Rubidium (see also http://www.
Mike Monett wrote:
> > Chris
>
> > The biggest problem with the OCXO is probably that it has a square
> > wave output.
>
> > With careful design it is possible to achieve a jitter of a few
> > tens of femtosec for a logic level output from a limiter, but the
> > OCXO designers are u
Bruce Griffiths wrote:
> Some ECL devices have jitter specs in the 100 to 200fsec range.
> see:
> http://www.onsemi.com
>
This is misleading. While it is true that they have this
low jitter at multi-Gb/s rates, the jitter is much greater
than this at lower clock rates. At 10 MHz, ECL devices
Rick
The following NIST paper indicates that the conventional wisdom on ECL
phase noise levels appear to be incorrect at least for some ECL divider
configurations:
http://www.am1.us/Papers/U11605%20Low%20Noise%20Synthesis-%20Walls.pdf
Waveform symmetry and low power supply noise seem to be very
Awesome... Thanks for being a sounding wall everyone
Indeed I am using the SRCs from TI for both the 2 DACs and the single
ADC...
The 127dB discrete ADCs out there are approximately half bit more in
dyn range than the 124dB core in the ADC... Indeed, there probably is
some significant
Just for the sake of indexing the archives, I'm sending this message to
point out the correct subject line of my immediately previous message (Thu
Apr 23 04:19:39 UTC 2009). I always hate it when mail has the digest
header instead of the real subject, then I went and did it myself.
--
Chris Caud
Hey Chris,
Thanks for the response... notes below
On Apr 23, 2009, at 12:19 AM, Chris Caudle wrote:
I'm a little late following up on this, but hopefully not too out of
context.
On Wed, April 8, 2009 10:23 pm, Chris Mack wrote:
The box / design of interest has ADCs, DACs, and a 38.88MHz O
By the way, I'm a little new to the list, someone give me and Chris M. a
nudge if this gets a little too audio-specialized and you want us to take
this off list.
> The Silicon Labs DSPLL(TM) chip is a 3 port device...
I'm pretty familiar with the SiLabs devices, those are the ones I
investigated
[Another late reply -- Easter and taxes got in the way]
At 09:59 -0400 09-04-2009, Chris Mack / N1SKY wrote:
Imagine this: if you were the mastering engineer for Elvis 50 years
ago, and if today's digital technology was available back then, would
you want to archive the King's record inside Iro
Folks, thanks for your input and sanity checking. To recap...
Having never worked with crystals before (only 2 and 10 GHz stuff in
GaAs power amp RFIC design for cell phone and the like using lab RF
generators or Vitesse / AMCC asics with clock recovery already done by
someone/something e
40 matches
Mail list logo