So to summarise : To make a synthesiser`s phase noise low :
- Apply the KIS principle [Keep It Simple]
- Use high speed [non-saturating?] logic rather than low
CMOS is actually among the cleanest logic families for digital PLLs these
days. ECL has always been among the worst. It was used
For digital circuits, it would seem that the potential for
metastability threshold uncertainty, is reduced when the
slope-to-noise ratio is optimized. I wonder if this concept is, or can
be quantified?
I don't think noise hurts or helps metastability. For every case where it
might hurt
Hal Murray wrote:
For digital circuits, it would seem that the potential for
metastability threshold uncertainty, is reduced when the
slope-to-noise ratio is optimized. I wonder if this concept is, or can
be quantified?
I don't think noise hurts or helps metastability. For every case
Hal,
The HP 8160/61A boxes appear on *Bay fairly often.
The HP8130/31A are there infrequently, but worth
having.
Pete Rawson
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Behalf Of Don Collie jnr
Sent: Sunday, April 27, 2008 11:03 PM
To: time-nuts@febo.com
Subject: [time-nuts] Phase noise Jitter
Hi Ulrich and Bruce,
OK Ulrich, so one way to combat jitter is to use logic with...
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To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Phase noise Jitter
If you haven't seen this yet:
http://www.ke5fx.com/HP_PN_seminar.pdf (7 MB)
... I'd strongly encourage you to check it out. The early
part of the document answers some of those questions pretty well
Don Collie jnr wrote:
I`m sorry, but I don`t understand what you mean in your second sentence
Bruce.
Thankyou for your comments, both!Don C.
Don
Rephrasing:
A VCO with a higher phase noise floor will have after division a higher
close in phase noise than a VCO
Don,
One effect I have observed on uP clock generators is that
fully differential circuits which utilize the crossover of
complementary signals are capable of lower jitter performance
than single ended circuits. At least 2 performance gains are
obvious;
1) the effective p-p swings are doubled
2)
Hello Bruce and all,
OK, now I think I understand : the more phase noise on the VCO, the more
jitter on the output of the divide by N.
This output spectrum comprises *only* the PRF+ close-in noise sidebands
[plus harmonics, and their noise sidebands]. Since the lowest frequency
Hi Don,
Any comparator or slicer has a noise density and a noise bandwidth.
The noise value of this slicer is the integral of the noise density
over the noise bandwidth. The noise bandwidth is the slicer
bandwidth, not the slicer frequency. Due to the slope, thus the slew
rate, of the
Don
Don Collie jnr wrote:
Hello Bruce and all,
OK, now I think I understand : the more phase noise on the VCO, the more
jitter on the output of the divide by N.
This output spectrum comprises *only* the PRF+ close-in noise sidebands
[plus harmonics, and their noise sidebands]. Since
Henk ten Pierick wrote:
Hi Don,
Any comparator or slicer has a noise density and a noise bandwidth.
The noise value of this slicer is the integral of the noise density
over the noise bandwidth. The noise bandwidth is the slicer
bandwidth, not the slicer frequency. Due to the slope,
Don Collie jnr wrote:
Hello Bruce and all,
OK, now I think I understand : the more phase noise on the VCO, the more
jitter on the output of the divide by N.
This output spectrum comprises *only* the PRF+ close-in noise sidebands
[plus harmonics, and their noise sidebands]. Since the
So to summarise : To make a synthesiser`s phase noise low :
- Apply the KIS principle [Keep It Simple]
- Use high speed [non-saturating?] logic rather than low
- The logic supplies should be well regulated, distributed
and decoupled.
- Make the PRF to the P/F detector as high as
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