Hi Ben,
El Thu, Jan 21, 2010 at 11:36:41PM -0800 Ben Warren ha dit:
On Thu, Jan 21, 2010 at 10:18 PM, Matthias Kaehlcke
matth...@kaehlcke.net wrote:
El Thu, Jan 21, 2010 at 06:01:47PM -0500 Mike Frysinger ha dit:
On Thursday 21 January 2010 16:29:24 Matthias Kaehlcke
Hi,
any comments on this?
On Wed, Dec 09, 2009 at 05:00:11PM +0100, Wolfgang Wegner wrote:
More tightly integrated non-blocking variants of some CFI flash access
functions. Enable with CONFIG_SYS_FLASH_CFI_NONBLOCK
These can be useful to erase flash or write complete sectors of flash
during
A newer CPLD version on the 405EX evaluation board requires a different
EBC controller setup for the CPLD register access. This patch now adds
a CPLD version detection for Kilauea and code to reconfigure the EBC
controller (chip select 2) for the new CPLD.
Additionally the CPLD version is printed
Dear Mike Frysinger,
In message 201001211932.19024.vap...@gentoo.org you wrote:
flash.h: pull in common.h for types
I don't have this one on my list; I understood you dropped it.
the last post was a question: were you planning on merging it. i'd prefer
you
did ;), but i'll let it
Dear Mike Frysinger,
In message 201001211934.21010.vap...@gentoo.org you wrote:
Hm... please let's not invent a new style to configure commands -
please use CONFIG_CMD_BOOTM instead (enabled by default).
i did it this way because u-boot doesnt have a default list for everyone of
Dear Wolfgang Wegner,
In message 20100122100332.gk23...@leila.ping.de you wrote:
On Wed, Dec 09, 2009 at 05:00:11PM +0100, Wolfgang Wegner wrote:
More tightly integrated non-blocking variants of some CFI flash access
functions. Enable with CONFIG_SYS_FLASH_CFI_NONBLOCK
These can be
A newer CPLD version on the 405EX evaluation board requires a different
EBC controller setup for the CPLD register access. This patch now adds
a CPLD version detection for Kilauea and code to reconfigure the EBC
controller (chip select 2) for the new CPLD.
Additionally the CPLD version is printed
Content of the RSR is put into gd early so we can output it together
with the CPU info. The clearing of gd in board_init_f is redundant for
this architecture as it is done in cpu_init_f so we remove it.
Signed-off-by: Detlev Zundel d...@denx.de
---
cpu/mpc512x/cpu.c |3 ++-
lib_ppc/board.c
Dear Stefan Roese,
In message 1264162912-21791-1-git-send-email...@denx.de you wrote:
A newer CPLD version on the 405EX evaluation board requires a different
EBC controller setup for the CPLD register access. This patch now adds
a CPLD version detection for Kilauea and code to reconfigure the
Dear Detlev Zundel,
In message 1264164180-10813-1-git-send-email-...@denx.de you wrote:
Content of the RSR is put into gd early so we can output it together
with the CPU info. The clearing of gd in board_init_f is redundant for
this architecture as it is done in cpu_init_f so we remove it.
A newer CPLD version on the 405EX evaluation board requires a different
EBC controller setup for the CPLD register access. This patch adds a CPLD
version detection for Kilauea and code to reconfigure the EBC controller
(chip select 2) for the old CPLD if no new version is found.
Additionally the
Hi Andreas,
I try to unzip a WinCE kernel with the U-Boot gunzip routine. It is working,
but it takes roughly 1min to uncompress a 10MB zip file.
I am working with a PXA270 platform. What could be the reason for the worst
performance?
Very likely the disabled instruction and data caches.
Hi Detlev,
thanks for the fast response. How do I enable data caches?
Regards,
Andreas
-Ursprüngliche Nachricht-
Von: Detlev Zundel [mailto:d...@denx.de]
Gesendet: Freitag, 22. Januar 2010 15:45
An: A. Geisreiter
Cc: u-boot@lists.denx.de
Betreff: Re: [U-Boot] Performance problems with
Hi Andreas,
thanks for the fast response. How do I enable data caches?
I fear this is not as easy as flipping a bit in a register. Depending
on the platform caches tend to be tied to the MMU, so enabling the
caches require setting up correct data structures for the MMU to work.
That's the
I fear this is not as easy as flipping a bit in a register. Depending
on the platform caches tend to be tied to the MMU, so enabling the
caches require setting up correct data structures for the MMU to work.
That's the non-trivial work.
Not that difficult, either. You just need to fill the
Hi Alessandro,
I fear this is not as easy as flipping a bit in a register. Depending
on the platform caches tend to be tied to the MMU, so enabling the
caches require setting up correct data structures for the MMU to work.
That's the non-trivial work.
Not that difficult, either.
I never
On Wed, Jul 29, 2009 at 6:05 AM, Giuseppe CONDORELLI
giuseppe.condore...@st.com wrote:
This patch updates zlib to the latest stable version.
Only relevant zlib parts were ported to u-boot tree, as already did for the
current zlib (0.95). New zlib guarantees a faster inflate performances
other
Hallo Detlev,
thanks for prompt reply and the input.
Regards,
Balaji KUPPUSAMY, PMP®
- Original Message
From: Detlev Zundel d...@denx.de
To: K Balaji krb_bal...@yahoo.com
Cc: u-boot@lists.denx.de; Daniel Hellstrom dan...@gaisler.com
Sent: Thu, January 21, 2010 2:14:52 PM
Subject:
Thanks Daniel,
it will be veryhelpful for me to start exploring. pleas do let me know once you
have updated for LEON3FT.
have nice weekend.
Regards,
Balaji KUPPUSAMY, PMP®
- Original Message
From: Daniel Hellstrom dan...@gaisler.com
To: K Balaji krb_bal...@yahoo.com
Cc:
Wolfgang Denk:
I don't like to see such heavy copying of code. This is a clear
indication that we should factor out the common parts
While I disagree (as explained), I'm trying hard to do
it. Unfortunately what is currently a Makefile decision (COBJS-y and
such) will sometimes become ifdef in
Dear Timur Tabi,
In message ed82fe3e1001220908j5887b625te5efd2b432891...@mail.gmail.com you
wrote:
This patch has broken MPC8610. I discovered it with git bisect.
After applying this patch, I get this error when I try to boot the
kernel:
Uncompressing Kernel Image ... Error: inflate()
Wolfgang Denk wrote:
What is your exact boot command? Eventually you are just using a too
low load address?
bootm 100 - c0
It's possible my addresses are bad, but I tried some other addresses and it
didn't fix anything. I may still be using bad addresses
= print bootcmd
Rick Bronson wrote:
Hi Sbabic,
Hi Rick,
I have the u-boot from the freescale ltib tar ball but it doesn't
seem to run too well. I comes up but when I press any keys nothing
happens. Anyway, I was wondering if you have anything newer that I
could try.
Please send your questions to
The list of 4xx SoCs that should send type 1 PCI transactions
is not defined correctly. As a result PCI-PCI bridges and devices
behind them are not identified. The following 4xx variants should
send type 1 transactions: 440GX, 440GP, 440SP, 440SPE, 460EX and 460GT.
Signed-off-by: Felix Radensky
I never said it was difficult, only non-trivial :)
Not trivial, actually.
I am looking forward to something like this for a long time now and I'm
sure other people will value it too, so thanks in advance!
It's still not working, but _I_ am working on it again after the weekend.
/alessandro
Hi
Can someone please let me know which ELDK supports P2020/P2010 (Freescale)
processors?
Thanks in advance
Vinay
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